| Line 91... |
Line 91... |
input fifo_tx_f_full,
|
input fifo_tx_f_full,
|
input fifo_tx_f_empty,
|
input fifo_tx_f_empty,
|
input [DWIDTH-1:0] fifo_tx_data_out,
|
input [DWIDTH-1:0] fifo_tx_data_out,
|
|
|
//INTERFACE WITH FIFO RECEIVER
|
//INTERFACE WITH FIFO RECEIVER
|
input fifo_rx_wr_en,
|
|
input fifo_rx_f_full,
|
input fifo_rx_f_full,
|
input fifo_rx_f_empty,
|
input fifo_rx_f_empty,
|
output [DWIDTH-1:0] fifo_rx_data_in,
|
output reg fifo_rx_wr_en,
|
|
output reg [DWIDTH-1:0] fifo_rx_data_in,
|
|
|
//INTERFACE WITH REGISTER CONFIGURATION
|
//INTERFACE WITH REGISTER CONFIGURATION
|
input [AWIDTH-1:0] DATA_CONFIG_REG,
|
input [AWIDTH-1:0] DATA_CONFIG_REG,
|
|
|
//INTERFACE TO APB AND READ FOR FIFO TX
|
//INTERFACE TO APB AND READ FOR FIFO TX
|
| Line 117... |
Line 117... |
//THIS IS USED TO GENERATE INTERRUPTIONS
|
//THIS IS USED TO GENERATE INTERRUPTIONS
|
assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;
|
assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;
|
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
|
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
|
|
|
//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM
|
//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM
|
reg [1:0] count;
|
reg [1:0] count_tx;
|
|
|
//CONTROL CLOCK AND COUNTER
|
//CONTROL CLOCK AND COUNTER
|
reg [11:0] count_send_data;
|
reg [11:0] count_send_data;
|
reg BR_CLK_O;
|
reg BR_CLK_O;
|
reg SDA_OUT;
|
reg SDA_OUT;
|
|
|
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
|
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
|
reg RESPONSE;
|
reg RESPONSE;
|
|
|
|
|
|
|
// TX PARAMETERS USED TO STATE MACHINE
|
// TX PARAMETERS USED TO STATE MACHINE
|
|
|
localparam [5:0] TX_IDLE = 6'd0, //IDLE
|
localparam [5:0] TX_IDLE = 6'd0, //IDLE
|
|
|
TX_START = 6'd1,//START BIT
|
TX_START = 6'd1,//START BIT
|
| Line 188... |
Line 185... |
//STATE CONTROL
|
//STATE CONTROL
|
reg [5:0] state_tx;
|
reg [5:0] state_tx;
|
reg [5:0] next_state_tx;
|
reg [5:0] next_state_tx;
|
|
|
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
|
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
|
/*
|
|
TODO:
|
|
We still working on verilog and we no have RX yet. So conections may change in time we are making progress on source code.
|
|
|
|
*/
|
|
assign SDA = SDA_OUT;
|
assign SDA = SDA_OUT;
|
assign SCL = BR_CLK_O;
|
assign SCL = BR_CLK_O;
|
|
|
//STANDARD ERROR
|
//STANDARD ERROR
|
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
|
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
|
| Line 678... |
Line 670... |
next_state_tx = TX_DELAY_BYTES;
|
next_state_tx = TX_DELAY_BYTES;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
if(count == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
next_state_tx = TX_ADRESS_1;
|
next_state_tx = TX_ADRESS_1;
|
end
|
end
|
else if(count == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
next_state_tx = TX_DATA0_1;
|
next_state_tx = TX_DATA0_1;
|
end
|
end
|
else if(count == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
next_state_tx = TX_DATA1_1;
|
next_state_tx = TX_DATA1_1;
|
end
|
end
|
else if(count == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
next_state_tx = TX_STOP;
|
next_state_tx = TX_STOP;
|
end
|
end
|
|
|
end
|
end
|
| Line 706... |
Line 698... |
begin
|
begin
|
next_state_tx = TX_NACK;
|
next_state_tx = TX_NACK;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(count == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
next_state_tx = TX_CONTROLIN_1;
|
next_state_tx = TX_CONTROLIN_1;
|
end
|
end
|
else if(count == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
next_state_tx = TX_ADRESS_1;
|
next_state_tx = TX_ADRESS_1;
|
end
|
end
|
else if(count == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
next_state_tx = TX_DATA0_1;
|
next_state_tx = TX_DATA0_1;
|
end
|
end
|
else if(count == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
next_state_tx = TX_DATA1_1;
|
next_state_tx = TX_DATA1_1;
|
end
|
end
|
end
|
end
|
end
|
end
|
| Line 743... |
Line 735... |
end
|
end
|
endcase
|
endcase
|
|
|
|
|
end
|
end
|
//SEQUENTIAL
|
//SEQUENTIAL TX
|
always@(posedge PCLK)
|
always@(posedge PCLK)
|
begin
|
begin
|
|
|
//RESET SYNC
|
//RESET SYNC
|
if(!PRESETn)
|
if(!PRESETn)
|
| Line 755... |
Line 747... |
//SIGNALS MUST BE RESETED
|
//SIGNALS MUST BE RESETED
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
state_tx <= TX_IDLE;
|
state_tx <= TX_IDLE;
|
SDA_OUT<= 1'b1;
|
SDA_OUT<= 1'b1;
|
fifo_tx_rd_en <= 1'b0;
|
fifo_tx_rd_en <= 1'b0;
|
count <= 2'd0;
|
count_tx <= 2'd0;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
RESPONSE<= 1'b0;
|
RESPONSE<= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
| Line 808... |
Line 800... |
end
|
end
|
|
|
if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
|
if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
|
begin
|
begin
|
SDA_OUT<=fifo_tx_data_out[0:0];
|
SDA_OUT<=fifo_tx_data_out[0:0];
|
|
count_tx <= 2'd0;
|
end
|
end
|
|
|
end
|
end
|
TX_CONTROLIN_1:
|
TX_CONTROLIN_1:
|
begin
|
begin
|
| Line 1763... |
Line 1756... |
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
|
|
if(count == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
count <= count + 2'd1;
|
count_tx <= count_tx + 2'd1;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[8:8];
|
SDA_OUT<=fifo_tx_data_out[8:8];
|
end
|
end
|
else if(count == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
count <= count + 2'd1;
|
count_tx <= count_tx + 2'd1;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[16:16];
|
SDA_OUT<=fifo_tx_data_out[16:16];
|
end
|
end
|
else if(count == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
count <= count + 2'd1;
|
count_tx <= count_tx + 2'd1;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[24:24];
|
SDA_OUT<=fifo_tx_data_out[24:24];
|
end
|
end
|
else if(count == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
count <= 2'd0;
|
count_tx <= 2'd0;
|
end
|
end
|
|
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
|
|
end
|
end
|
| Line 1801... |
Line 1794... |
|
|
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
|
if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
|
begin
|
begin
|
count_send_data <= count_send_data + 12'd1;
|
count_send_data <= count_send_data + 12'd1;
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
|
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
|
begin
|
begin
|
SDA_OUT<=1'b0;
|
SDA_OUT<=1'b0;
|
end
|
end
|
else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
|
else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
| Line 1814... |
Line 1807... |
else if(count_send_data == DATA_CONFIG_REG[13:2]*2'd2)
|
else if(count_send_data == DATA_CONFIG_REG[13:2]*2'd2)
|
begin
|
begin
|
SDA_OUT<=1'b0;
|
SDA_OUT<=1'b0;
|
end
|
end
|
|
|
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
|
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
|
begin
|
begin
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
end
|
end
|
else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
|
else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
|
begin
|
begin
|
| Line 1832... |
Line 1825... |
end
|
end
|
else
|
else
|
begin
|
begin
|
count_send_data <= 12'd0;
|
count_send_data <= 12'd0;
|
|
|
if(count == 2'd0)
|
if(count_tx == 2'd0)
|
begin
|
begin
|
count <= 2'd0;
|
count_tx <= 2'd0;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[0:0];
|
SDA_OUT<=fifo_tx_data_out[0:0];
|
end
|
end
|
else if(count == 2'd1)
|
else if(count_tx == 2'd1)
|
begin
|
begin
|
count <= 2'd1;
|
count_tx <= 2'd1;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[8:8];
|
SDA_OUT<=fifo_tx_data_out[8:8];
|
end
|
end
|
else if(count == 2'd2)
|
else if(count_tx == 2'd2)
|
begin
|
begin
|
count <= 2'd2;
|
count_tx <= 2'd2;
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
SDA_OUT<=fifo_tx_data_out[16:16];
|
SDA_OUT<=fifo_tx_data_out[16:16];
|
end
|
end
|
else if(count == 2'd3)
|
else if(count_tx == 2'd3)
|
begin
|
begin
|
BR_CLK_O <= 1'b1;
|
BR_CLK_O <= 1'b1;
|
count <= 2'd3;
|
count_tx <= 2'd3;
|
SDA_OUT<=fifo_tx_data_out[24:24];
|
SDA_OUT<=fifo_tx_data_out[24:24];
|
end
|
end
|
|
|
|
|
end
|
end
|
| Line 1893... |
Line 1886... |
|
|
|
|
end
|
end
|
|
|
|
|
|
// RX PARAMETERS USED TO STATE MACHINE
|
|
|
|
localparam [5:0] RX_IDLE = 6'd0, //IDLE
|
|
|
|
RX_START = 6'd1,//START BIT
|
|
|
|
RX_CONTROLIN_1 = 6'd2, //START BYTE
|
|
RX_CONTROLIN_2 = 6'd3,
|
|
RX_CONTROLIN_3 = 6'd4,
|
|
RX_CONTROLIN_4 = 6'd5,
|
|
RX_CONTROLIN_5 = 6'd6,
|
|
RX_CONTROLIN_6 = 6'd7,
|
|
RX_CONTROLIN_7 = 6'd8,
|
|
RX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
|
|
|
|
RX_RESPONSE_CIN =6'd10, //RESPONSE
|
|
|
|
RX_ADRESS_1 = 6'd11,//START BYTE
|
|
RX_ADRESS_2 = 6'd12,
|
|
RX_ADRESS_3 = 6'd13,
|
|
RX_ADRESS_4 = 6'd14,
|
|
RX_ADRESS_5 = 6'd15,
|
|
RX_ADRESS_6 = 6'd16,
|
|
RX_ADRESS_7 = 6'd17,
|
|
RX_ADRESS_8 = 6'd18,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_ADRESS =6'd19, //RESPONSE
|
|
|
|
RX_DATA0_1 = 6'd20,//START BYTE
|
|
RX_DATA0_2 = 6'd21,
|
|
RX_DATA0_3 = 6'd22,
|
|
RX_DATA0_4 = 6'd23,
|
|
RX_DATA0_5 = 6'd24,
|
|
RX_DATA0_6 = 6'd25,
|
|
RX_DATA0_7 = 6'd26,
|
|
RX_DATA0_8 = 6'd27,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
|
|
|
|
RX_DATA1_1 = 6'd29,//START BYTE
|
|
RX_DATA1_2 = 6'd30,
|
|
RX_DATA1_3 = 6'd31,
|
|
RX_DATA1_4 = 6'd32,
|
|
RX_DATA1_5 = 6'd33,
|
|
RX_DATA1_6 = 6'd34,
|
|
RX_DATA1_7 = 6'd35,
|
|
RX_DATA1_8 = 6'd36,//END FIRST BYTE
|
|
|
|
RX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
|
|
|
|
RX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
|
|
RX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
|
|
RX_STOP = 6'd40;//USED TO SEND STOP BIT
|
|
|
|
//STATE CONTROL
|
|
reg [5:0] state_rx;
|
|
reg [5:0] next_state_rx;
|
|
|
|
reg [11:0] count_receive_data;
|
|
|
|
reg [1:0] count_rx;
|
|
|
|
//COMBINATIONAL BLOCK RX
|
|
|
|
always@(*)
|
|
begin
|
|
|
|
|
|
next_state_rx = state_rx;
|
|
|
|
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
|
RX_IDLE:
|
|
begin
|
|
//OBEYING SPEC
|
|
if(DATA_CONFIG_REG[1] == 1'b0 && DATA_CONFIG_REG[0] == 1'b0)
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b1)
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
else if(DATA_CONFIG_REG[1] == 1'b1 && DATA_CONFIG_REG[0] == 1'b0 && SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
next_state_rx = RX_START;
|
|
end
|
|
end
|
|
RX_START:
|
|
begin
|
|
|
|
if(SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_START;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
end
|
|
RX_CONTROLIN_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_2;
|
|
end
|
|
end
|
|
RX_CONTROLIN_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_3;
|
|
end
|
|
end
|
|
RX_CONTROLIN_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_4;
|
|
end
|
|
end
|
|
RX_CONTROLIN_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_5;
|
|
end
|
|
end
|
|
RX_CONTROLIN_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_6;
|
|
end
|
|
end
|
|
RX_CONTROLIN_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_7;
|
|
end
|
|
end
|
|
RX_CONTROLIN_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
end
|
|
RX_CONTROLIN_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_CIN;
|
|
end
|
|
end
|
|
RX_RESPONSE_CIN:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_CIN;
|
|
end
|
|
end
|
|
|
|
RX_ADRESS_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_2;
|
|
end
|
|
end
|
|
RX_ADRESS_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_3;
|
|
end
|
|
end
|
|
RX_ADRESS_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_4;
|
|
end
|
|
end
|
|
RX_ADRESS_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_5;
|
|
end
|
|
end
|
|
RX_ADRESS_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_6;
|
|
end
|
|
end
|
|
RX_ADRESS_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_7;
|
|
end
|
|
end
|
|
RX_ADRESS_7:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_ADRESS_8;
|
|
end
|
|
|
|
end
|
|
RX_ADRESS_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_ADRESS_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_ADRESS;
|
|
end
|
|
end
|
|
RX_RESPONSE_ADRESS:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_ADRESS;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
end
|
|
|
|
RX_DATA0_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_2;
|
|
end
|
|
end
|
|
RX_DATA0_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_2;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_3;
|
|
end
|
|
end
|
|
RX_DATA0_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_4;
|
|
end
|
|
end
|
|
RX_DATA0_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_5;
|
|
end
|
|
end
|
|
RX_DATA0_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_6;
|
|
end
|
|
end
|
|
RX_DATA0_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_7;
|
|
end
|
|
end
|
|
RX_DATA0_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA0_8;
|
|
end
|
|
end
|
|
RX_DATA0_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA0_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA0_1;
|
|
end
|
|
end
|
|
RX_RESPONSE_DATA0_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA0_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
end
|
|
RX_DATA1_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_2;
|
|
end
|
|
end
|
|
RX_DATA1_2:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_3;
|
|
end
|
|
end
|
|
RX_DATA1_3:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_3;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_4;
|
|
end
|
|
end
|
|
RX_DATA1_4:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_4;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_5;
|
|
end
|
|
end
|
|
RX_DATA1_5:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_5;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_6;
|
|
end
|
|
end
|
|
RX_DATA1_6:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_6;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_7;
|
|
end
|
|
end
|
|
RX_DATA1_7:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_7;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DATA1_8;
|
|
end
|
|
end
|
|
RX_DATA1_8:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DATA1_8;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA1_1;
|
|
end
|
|
end
|
|
RX_RESPONSE_DATA1_1:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_RESPONSE_DATA1_1;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_DELAY_BYTES;
|
|
end
|
|
end
|
|
RX_DELAY_BYTES:
|
|
begin
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_DELAY_BYTES;
|
|
end
|
|
else
|
|
begin
|
|
|
|
if(count_rx == 2'd0)
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else if(count_rx == 2'd1)
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else if(count_rx == 2'd2)
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
else if(count_rx == 2'd3)
|
|
begin
|
|
next_state_rx = RX_STOP;
|
|
end
|
|
|
|
end
|
|
end
|
|
RX_NACK:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2]*2'd2)
|
|
begin
|
|
next_state_rx = RX_NACK;
|
|
end
|
|
else
|
|
begin
|
|
if(count_rx == 2'd0)
|
|
begin
|
|
next_state_rx = RX_CONTROLIN_1;
|
|
end
|
|
else if(count_rx == 2'd1)
|
|
begin
|
|
next_state_rx = RX_ADRESS_1;
|
|
end
|
|
else if(count_rx == 2'd2)
|
|
begin
|
|
next_state_rx = RX_DATA0_1;
|
|
end
|
|
else if(count_rx == 2'd3)
|
|
begin
|
|
next_state_rx = RX_DATA1_1;
|
|
end
|
|
end
|
|
|
|
|
|
end
|
|
RX_STOP:
|
|
begin
|
|
|
|
if(count_receive_data != DATA_CONFIG_REG[13:2])
|
|
begin
|
|
next_state_rx = RX_STOP;
|
|
end
|
|
else
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
|
|
end
|
|
default:
|
|
begin
|
|
next_state_rx = RX_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
|
|
//SEQUENTIAL BLOCK RX
|
|
|
|
always@(posedge PCLK)
|
|
begin
|
|
|
|
if(!PRESETn)
|
|
begin
|
|
//SIGNALS MUST BE RESETED
|
|
count_receive_data <= 12'd0;
|
|
state_rx <= RX_IDLE;
|
|
fifo_rx_wr_en <= 1'b0;
|
|
count_rx <= 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
|
|
state_rx <= next_state_rx;
|
|
|
|
case(state_rx)//STATE_RX IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
|
|
RX_IDLE:
|
|
begin
|
|
if(SDA == 1'b0 && SCL == 1'b1)
|
|
begin
|
|
count_receive_data <= count_receive_data +12'd1;
|
|
end
|
|
else
|
|
begin
|
|
count_receive_data <= 12'd0;
|
|
end
|
|
end
|
|
RX_START:
|
|
begin
|
|
if(SDA == 1'b0 && SCL == 1'b0)
|
|
begin
|
|
count_receive_data <= count_receive_data +12'd1;
|
|
end
|
|
else
|
|
begin
|
|
count_receive_data <= 12'd0;
|
|
end
|
|
end
|
|
RX_CONTROLIN_1:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_2:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_3:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_4:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_5:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_6:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_7:
|
|
begin
|
|
|
|
end
|
|
RX_CONTROLIN_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_CIN:
|
|
begin
|
|
|
|
end
|
|
RX_ADRESS_1:
|
|
begin
|
|
end
|
|
RX_ADRESS_2:
|
|
begin
|
|
end
|
|
RX_ADRESS_3:
|
|
begin
|
|
end
|
|
RX_ADRESS_4:
|
|
begin
|
|
end
|
|
RX_ADRESS_5:
|
|
begin
|
|
end
|
|
RX_ADRESS_6:
|
|
begin
|
|
end
|
|
RX_ADRESS_7:
|
|
begin
|
|
end
|
|
RX_ADRESS_8:
|
|
begin
|
|
end
|
|
RX_RESPONSE_ADRESS:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_1:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_2:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_3:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_4:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_5:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_6:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_7:
|
|
begin
|
|
|
|
end
|
|
RX_DATA0_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_DATA0_1:
|
|
begin
|
|
end
|
|
|
|
RX_DATA1_1:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_2:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_3:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_4:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_5:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_6:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_7:
|
|
begin
|
|
|
|
end
|
|
RX_DATA1_8:
|
|
begin
|
|
|
|
end
|
|
RX_RESPONSE_DATA1_1:
|
|
begin
|
|
end
|
|
RX_DELAY_BYTES:
|
|
begin
|
|
|
|
end
|
|
RX_NACK:
|
|
begin
|
|
|
|
|
|
end
|
|
RX_STOP:
|
|
begin
|
|
|
|
|
|
end
|
|
default:
|
|
begin
|
|
count_receive_data <= 12'd4095;
|
|
fifo_rx_wr_en <= 1'b0;
|
|
count_rx <= 2'd3;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
