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[/] [apbtoaes128/] [trunk/] [pli/] [bfm_ecb/] [aes_bfm_key_generation_dma_ecb.h] - Diff between revs 4 and 5
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Rev 4 |
Rev 5 |
Line 362... |
Line 362... |
{
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{
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v_ecb.value.integer = ADDR_AES_KEYR0;
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v_ecb.value.integer = ADDR_AES_KEYR0;
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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}
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}
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if(counter_read == 4)
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{
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v_ecb.value.integer = ADDR_AES_IVR3;
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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}
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if(counter_read == 5)
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{
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v_ecb.value.integer = ADDR_AES_IVR2;
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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}
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if(counter_read == 6)
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{
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v_ecb.value.integer = ADDR_AES_IVR1;
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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}
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if(counter_read == 7)
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{
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v_ecb.value.integer = ADDR_AES_IVR0;
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vpi_put_value(PADDR, &v_ecb, NULL, vpiNoDelay);
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}
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v_ecb.value.integer = 0;
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v_ecb.value.integer = 0;
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vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
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vpi_put_value(PENABLE, &v_ecb, NULL, vpiNoDelay);
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counter = 0;
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counter = 0;
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}
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}
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if(counter_read == 4)
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if(counter_read == 8)
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{
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{
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STATE = RESET_SR;
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STATE = RESET_SR;
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counter_write = 0;
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counter_write = 0;
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counter_read = 0;
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counter_read = 0;
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}
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}
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