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[/] [apbtoaes128/] [trunk/] [rtl/] [control_unit.v] - Diff between revs 3 and 7

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Rev 3 Rev 7
Line 3... Line 3... 
////
 
////
 
////    AES CORE BLOCK
 
////    AES CORE BLOCK
 
////
 
////
 
////
 
////
 
////
 
////
 
//// This file is part of the APB to AES128 project
 
//// This file is part of the APB to I2C project
 
////
 
////
 
//// http://www.opencores.org/cores/apbtoaes128/
 
//// http://www.opencores.org/cores/apbi2c/
 
////
 
////
 
////
 
////
 
////
 
////
 
//// Description
 
//// Description
 
////
 
////
Line 86... Line 86... 
        output reg bypass_key_en,
 
        output reg bypass_key_en,
 
        output reg key_sel,
 
        output reg key_sel,
 
        output reg iv_cnt_en,
 
        output reg iv_cnt_en,
 
        output reg iv_cnt_sel,
 
        output reg iv_cnt_sel,
 
        output reg key_derivation_en,
 
        output reg key_derivation_en,
 
        output reg end_comp,
 
        output end_comp,
 
        output key_init,
 
        output key_init,
 
        output key_gen,
 
        output key_gen,
 
        output mode_ctr,
 
        output mode_ctr,
 
        output mode_cbc,
 
        output mode_cbc,
 
        output last_round,
 
        output last_round,
Line 231... Line 231... 
 
 
 
 
reg [3:0] state, next_state;
 
reg [3:0] state, next_state;
 
reg [3:0] rd_count;
 
reg [3:0] rd_count;
 
 
 
 
 
reg rd_count_en;
 
reg rd_count_en;
 
 
 
//reg end_aes_pp1, end_aes_pp2;
 
wire op_key_derivation;
 
wire op_key_derivation;
 
wire first_round;
 
wire first_round;
 
wire [1:0] op_mode;
 
wire [1:0] op_mode;
 
 
 
wire enc_dec;
 
 
 
 
 
// State Flops Definition
 
// State Flops Definition
 
always @(posedge clk, negedge rst_n)
 
always @(posedge clk, negedge rst_n)
 
        begin
 
        begin
 
                if(!rst_n)
 
                if(!rst_n)
Line 359... Line 361... 
                endcase
 
                endcase
 
        end
 
        end
 
 
 
 
 
 
 
 
 
// Output Logic
 
// Output Logic
 
 
 
assign end_comp = (state == READY)?ENABLE:DISABLE;
 
 
 
 
 
 
 
/*
 
 
 
always @(posedge clk, negedge rst_n)
 
 
 
begin
 
 
 
                if(!rst_n)
 
 
 
                begin
 
 
 
                        end_aes_pp1 <= 1'b0;
 
 
 
                        end_aes_pp2 <= 1'b0;
 
 
 
                        end_comp <= 1'b0;
 
 
 
                end
 
 
 
                else
 
 
 
                        if(state == READY)
 
 
 
                        begin
 
 
 
                                end_aes_pp1 <= ENABLE;
 
 
 
                                //end_aes_pp2 <= end_aes_pp1;
 
 
 
                                end_comp <= end_aes_pp1 ;
 
 
 
                        end
 
 
 
                        else
 
 
 
                        begin
 
 
 
                                end_aes_pp1 <= DISABLE;
 
 
 
                                //end_aes_pp2 <= end_aes_pp1;
 
 
 
                                end_comp <= end_aes_pp1 ;
 
 
 
                        end
 
 
 
 
 
 
 
end
 
 
 
*/
 
always @(*)
 
always @(*)
 
        begin
 
        begin
 
                sbox_sel = COL_0;
 
                sbox_sel = COL_0;
 
                rk_sel = COL;
 
                rk_sel = COL;
 
                bypass_rk = DISABLE;
 
                bypass_rk = DISABLE;
Line 374... Line 403... 
                rd_count_en = DISABLE;
 
                rd_count_en = DISABLE;
 
                iv_cnt_en = DISABLE;
 
                iv_cnt_en = DISABLE;
 
                iv_cnt_sel = IV_BUS;
 
                iv_cnt_sel = IV_BUS;
 
                bypass_key_en = DISABLE;
 
                bypass_key_en = DISABLE;
 
                key_derivation_en = DISABLE;
 
                key_derivation_en = DISABLE;
 
                end_comp = DISABLE;
 
                //end_comp = DISABLE;
 
                case(state)
 
                case(state)
 
                        ROUND0_COL0:
 
                        ROUND0_COL0:
 
                                begin
 
                                begin
 
                                        sbox_sel = COL_0;
 
                                        sbox_sel = COL_0;
 
                                        rk_sel   = COL;
 
                                        rk_sel   = COL;
Line 544... Line 573... 
                                        key_sel = KEY_OUT;
 
                                        key_sel = KEY_OUT;
 
                                        bypass_key_en = ENABLE;
 
                                        bypass_key_en = ENABLE;
 
                                end
 
                                end
 
                        READY:
 
                        READY:
 
                                begin
 
                                begin
 
                                        end_comp = ENABLE;
 
                                        //end_comp = ENABLE;
 
                                        if(op_mode == KEY_DERIVATION)
 
                                        if(op_mode == KEY_DERIVATION)
 
                                                key_derivation_en = ENABLE;
 
                                                key_derivation_en = ENABLE;
 
                                end
 
                                end
 
                endcase
 
                endcase
 
        end
 
        end

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