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https://opencores.org/ocsvn/apbtoaes128/apbtoaes128/trunk
[/] [apbtoaes128/] [trunk/] [rtl/] [data_swap.v] - Diff between revs 3 and 7
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Rev 7 |
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////
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//// AES CORE BLOCK
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//// AES CORE BLOCK
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//// This file is part of the APB to AES128 project
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//// This file is part of the APB to I2C project
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////
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//// http://www.opencores.org/cores/apbtoaes128/
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//// http://www.opencores.org/cores/apbi2c/
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////
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//// Description
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//// Description
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wire [WIDTH - 1 : 0] words[0 : TYPES - 1];
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wire [WIDTH - 1 : 0] words[0 : TYPES - 1];
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generate
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generate
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genvar i, j;
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genvar i, j;
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for(i = 0; i < TYPES; i = i + 1)
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for(i = 0; i < TYPES; i = i + 1)
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begin:BLOCK
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for(j = 0; j < WIDTH; j = j + 1)
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for(j = 0; j < WIDTH; j = j + 1)
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begin
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begin: SUB_BLOCK
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if(i != 3)
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if(i != 3)
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assign words[i][j] = data_in[(WIDTH - (WIDTH/2**i)) - 2*(WIDTH/2**i)*(j/(WIDTH/2**i)) + j];
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assign words[i][j] = data_in[(WIDTH - (WIDTH/2**i)) - 2*(WIDTH/2**i)*(j/(WIDTH/2**i)) + j];
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else
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else
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assign words[i][j] = data_in[WIDTH - 1 - j];
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assign words[i][j] = data_in[WIDTH - 1 - j];
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end
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end
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end
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endgenerate
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endgenerate
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assign data_swap = words[swap_type];
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assign data_swap = words[swap_type];
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endmodule
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endmodule
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