Subversion Repositories apbtoaes128

reg [ 1 : 0] rk_sel_pp1;

reg [ 1 : 0] rk_sel_pp1;

reg [ 1 : 0] rk_sel_pp2;

reg [ 1 : 0] rk_sel_pp2;

reg key_sel_pp1;

reg key_sel_pp1;

reg rk_out_sel_pp1, rk_out_sel_pp2;

reg rk_out_sel_pp1, rk_out_sel_pp2;

reg last_round_pp1, last_round_pp2;

reg last_round_pp1, last_round_pp2;

assign key_bus = key_mux_out;

assign key_bus = key_mux_out;

assign iv_bus = iv_mux_out;

assign iv_bus = iv_mux_out;

// Input Swap Unit

// Input Swap Unit

                                else

                                else

                                begin

                                begin

                                                if(l == 3)

                                                if(l == 3)

                                                begin

                                                begin

                                                                if(iv_en[l] || iv_cnt_en)

                                                                if(iv_en[l] || iv_cnt_en)

                                                                        iv[l] <= (iv_cnt_sel) ? iv[l] : bus_in;

                                                                        iv[l] <= (iv_cnt_sel) ? iv[l] : bus_in;

                                                end

                                                end

                                                else

                                                else

                                                begin

                                                begin

                                                                if(iv_en[l])

                                                                if(iv_en[l])

                                                                        iv[l] <= bus_in;

                                                                        iv[l] <= bus_in;

                                                end

                                                end

assign add_rk_sel = (bypass_rk) ? rk_out_sel : rk_out_sel_pp2;

assign add_rk_sel = (bypass_rk) ? rk_out_sel : rk_out_sel_pp2;

assign add_rk_out = (add_rk_sel) ? add_rd : (last_round_pp2 ? sbox_pp2 : mix_out_dec);

assign add_rk_out = (add_rk_sel) ? add_rd : (last_round_pp2 ? sbox_pp2 : mix_out_dec);

// Pipeline Registers for Control Signals

// Pipeline Registers for Control Signals

always @(posedge clk, negedge rst_n)

always @(posedge clk, negedge rst_n)

        begin

        begin

                if(!rst_n)

                if(!rst_n)

                                last_round_pp1 <= last_round;

                                last_round_pp1 <= last_round;

                                last_round_pp2 <= last_round_pp1;

                                last_round_pp2 <= last_round_pp1;

                                //end_aes_pp1 <= end_comp;

                                //end_aes_pp1 <= end_comp;

                        end

                        end

        end

        end

endmodule

endmodule

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