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Subversion Repositories apbtoaes128

[/] [apbtoaes128/] [trunk/] [rtl/] [datapath.v] - Diff between revs 3 and 7

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Rev 3 Rev 7
Line 3... Line 3... 
////
 
////
 
////    AES CORE BLOCK
 
////    AES CORE BLOCK
 
////
 
////
 
////
 
////
 
////
 
////
 
//// This file is part of the APB to AES128 project
 
//// This file is part of the APB to I2C project
 
////
 
////
 
//// http://www.opencores.org/cores/apbtoaes128/
 
//// http://www.opencores.org/cores/apbi2c/
 
////
 
////
 
////
 
////
 
////
 
////
 
//// Description
 
//// Description
 
////
 
////
Line 239... Line 239... 
reg [ 1 : 0] rk_sel_pp1;
 
reg [ 1 : 0] rk_sel_pp1;
 
reg [ 1 : 0] rk_sel_pp2;
 
reg [ 1 : 0] rk_sel_pp2;
 
reg key_sel_pp1;
 
reg key_sel_pp1;
 
reg rk_out_sel_pp1, rk_out_sel_pp2;
 
reg rk_out_sel_pp1, rk_out_sel_pp2;
 
reg last_round_pp1, last_round_pp2;
 
reg last_round_pp1, last_round_pp2;
 
reg end_aes_pp1, end_aes_pp2;
 
//reg end_aes_pp2;//end_aes_pp1, end_aes_pp2;
 
 
 
 
 
assign key_bus = key_mux_out;
 
assign key_bus = key_mux_out;
 
assign iv_bus = iv_mux_out;
 
assign iv_bus = iv_mux_out;
 
 
 
 
 
// Input Swap Unit
 
// Input Swap Unit
Line 300... Line 300... 
 
 
 
 
 
 
 
 
// IV and BKP Registers
 
// IV and BKP Registers
 
generate
 
generate
 
        genvar l;
 
        genvar l;
 
 
 
 
 
        for(l = 0; l < 4; l = l + 1)
 
        for(l = 0; l < 4; l = l + 1)
 
 
 
        begin
 
                always @(posedge clk, negedge rst_n)
 
                always @(posedge clk, negedge rst_n)
 
                        begin
 
                        begin
 
                                if(!rst_n)
 
                                if(!rst_n)
 
                                        begin
 
                                        begin
 
                                                iv[l]    <= {32{1'b0}};
 
                                                iv[l]    <= {32{1'b0}};
Line 323... Line 325... 
                                                                if(iv_en[l])
 
                                                                if(iv_en[l])
 
                                                                        iv[l] <= bus_in;
 
                                                                        iv[l] <= bus_in;
 
                                                        end
 
                                                        end
 
 
 
 
 
                                        if(bkp_en[l])
 
                                        if(bkp_en[l])
 
                                                bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in : bkp_1[l]);
 
                                                //bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in : bkp_1[l]);
 
 
 
                                                bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in[32*(l + 1) - 1 : 32*l] : bkp_1[l]);
 
 
 
 
 
                                        if(bkp_en[l])
 
                                        if(bkp_en[l])
 
                                                bkp_1[l] <= col_in;
 
                                                bkp_1[l] <= col_in[32*(l + 1) - 1 : 32*l];
 
                                        end
 
                                        end
 
                        end
 
                        end
 
 
 
 
 
 
 
                end
 
endgenerate
 
endgenerate
 
 
 
 
 
assign col_sel_w_bypass = (bypass_rk) ? col_sel : col_sel_pp2;
 
assign col_sel_w_bypass = (bypass_rk) ? col_sel : col_sel_pp2;
 
 
 
 
 
// Columns Input Multiplexors
 
// Columns Input Multiplexors
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assign add_rk_sel = (bypass_rk) ? rk_out_sel : rk_out_sel_pp2;
 
assign add_rk_sel = (bypass_rk) ? rk_out_sel : rk_out_sel_pp2;
 
 
 
 
 
assign add_rk_out = (add_rk_sel) ? add_rd : (last_round_pp2 ? sbox_pp2 : mix_out_dec);
 
assign add_rk_out = (add_rk_sel) ? add_rd : (last_round_pp2 ? sbox_pp2 : mix_out_dec);
 
 
 
 
 
assign end_aes = end_aes_pp2;
 
assign end_aes = end_comp;//end_aes_pp2;
 
 
 
 
 
// Pipeline Registers for Control Signals
 
// Pipeline Registers for Control Signals
 
always @(posedge clk, negedge rst_n)
 
always @(posedge clk, negedge rst_n)
 
        begin
 
        begin
 
                if(!rst_n)
 
                if(!rst_n)
 
                        begin
 
                        begin
 
                                end_aes_pp1 <= DISABLE;
 
                                //end_aes_pp1 <= DISABLE;
 
                                end_aes_pp2 <= DISABLE;
 
                                //end_aes_pp2 <= DISABLE;
 
 
 
 
 
                                col_sel_pp1 <= INPUT;
 
                                col_sel_pp1 <= INPUT;
 
                                col_sel_pp2 <= INPUT;
 
                                col_sel_pp2 <= INPUT;
 
 
 
 
 
                                col_en_cnt_unit_pp1 <= COL_DIS;
 
                                col_en_cnt_unit_pp1 <= COL_DIS;
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                                rk_out_sel_pp2 <= rk_out_sel_pp1;
 
                                rk_out_sel_pp2 <= rk_out_sel_pp1;
 
 
 
 
 
                                last_round_pp1 <= last_round;
 
                                last_round_pp1 <= last_round;
 
                                last_round_pp2 <= last_round_pp1;
 
                                last_round_pp2 <= last_round_pp1;
 
 
 
 
 
                                end_aes_pp1 <= end_comp;
 
                                //end_aes_pp1 <= end_comp;
 
                                end_aes_pp2 <= end_aes_pp1;
 
                                //end_aes_pp2 <= end_comp;
 
                        end
 
                        end
 
        end
 
        end
 
endmodule
 
endmodule
 
 
 
 
 
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