| Line 197... |
Line 197... |
reg dma_req;
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reg dma_req;
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wire enable;
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wire enable;
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// Write and read enable signals
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// Write and read enable signals
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assign write_en = PSEL & PENABLE & PWRITE;
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assign write_en = PSEL & PENABLE & PWRITE;
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assign read_en = (PSEL & ~PWRITE & (ccf_set | ccf))?1'b1:
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assign read_en = (PSEL & ~PWRITE)?1'b1:1'b0;
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((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3 ))?1'b1:1'b0;
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//((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3))?1'b1:1'b0;
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// Configuration Register Logic
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// Configuration Register Logic
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assign dma_out_en = aes_cr[10];
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assign dma_out_en = aes_cr[10];
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assign dma_in_en = aes_cr[9];
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assign dma_in_en = aes_cr[9];
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assign err_ie = aes_cr[8];
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assign err_ie = aes_cr[8];
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| Line 271... |
Line 271... |
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// Computation Complete Flag
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// Computation Complete Flag
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if(ccf_set)
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if(ccf_set)
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ccf <= 1'b1;
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ccf <= 1'b1;
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else
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else
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if(ccfc && aes_cr_wr_en)// && access_permission)
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if(ccfc && aes_cr_wr_en && access_permission)
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ccf <= 1'b0;
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ccf <= 1'b0;
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end
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end
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end
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end
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// Interruption on erros Signals
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// Interruption on erros Signals
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assign int_ccf = ccf_ie & ccf_set;
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assign int_ccf = ccf_ie & ccf_set;
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| Line 427... |
Line 427... |
bus_out_mux = 32'd0;
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bus_out_mux = 32'd0;
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case(PADDR)
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case(PADDR)
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AES_CR:
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AES_CR:
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bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
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bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
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AES_SR:
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AES_SR:
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf && ~PENABLE)?1'b1:((ccf_set && PENABLE))?1'b0:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set && ~PENABLE)? 1'b1:(ccfc && aes_cr_wr_en)?1'b0:ccf};
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AES_DINR, AES_DOUTR:
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AES_DINR, AES_DOUTR:
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begin
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if(~PWRITE && PADDR == AES_DOUTR && (ccf_set || ccf ))
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bus_out_mux = col_bus;
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bus_out_mux = col_bus;
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end
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AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
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AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
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if(!enable)
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if(!enable)
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bus_out_mux = key_bus;
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bus_out_mux = key_bus;
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AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
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AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
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if(!enable)
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if(!enable)
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