| Line 198... |
Line 198... |
wire enable;
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wire enable;
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// Write and read enable signals
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// Write and read enable signals
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assign write_en = PSEL & PENABLE & PWRITE;
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assign write_en = PSEL & PENABLE & PWRITE;
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assign read_en = (PSEL & ~PWRITE)?1'b1:1'b0;
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assign read_en = (PSEL & ~PWRITE)?1'b1:1'b0;
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//((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3))?1'b1:1'b0;
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// Configuration Register Logic
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// Configuration Register Logic
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assign dma_out_en = aes_cr[10];
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assign dma_out_en = aes_cr[10];
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assign dma_in_en = aes_cr[9];
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assign dma_in_en = aes_cr[9];
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assign err_ie = aes_cr[8];
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assign err_ie = aes_cr[8];
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| Line 271... |
Line 270... |
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// Computation Complete Flag
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// Computation Complete Flag
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if(ccf_set)
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if(ccf_set)
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ccf <= 1'b1;
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ccf <= 1'b1;
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else
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else
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if(ccfc && aes_cr_wr_en && access_permission)
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if(ccfc && aes_cr_wr_en )//&& access_permission)
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ccf <= 1'b0;
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ccf <= 1'b0;
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end
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end
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end
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end
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// Interruption on erros Signals
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// Interruption on erros Signals
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assign int_ccf = ccf_ie & ccf_set;
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assign int_ccf = ccf_ie & ccf_set;
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| Line 401... |
Line 400... |
end
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end
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assign col_addr = cnt;
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assign col_addr = cnt;
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assign col_wr_en = (PADDR == AES_DINR && write_en && state == INPUT);
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assign col_wr_en = (PADDR == AES_DINR && write_en && state == INPUT);
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assign col_rd_en = (PADDR == AES_DOUTR && read_en && state == OUTPUT);
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assign col_rd_en = (PADDR == AES_DOUTR && read_en && state == OUTPUT);
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assign wr_err_en = (PADDR == AES_DINR && write_en && (state != INPUT && state != IDLE));
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assign wr_err_en = (PENABLE && PADDR == AES_DINR && write_en && (state != INPUT && state != IDLE));
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assign rd_err_en = (PADDR == AES_DOUTR && read_en && (state != OUTPUT && state != IDLE));
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assign rd_err_en = (PENABLE && PADDR == AES_DOUTR && read_en && (state != OUTPUT && state != IDLE));
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// DMA Requests Logic
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// DMA Requests Logic
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always @(posedge PCLK, negedge PRESETn)
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always @(posedge PCLK, negedge PRESETn)
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begin
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begin
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if(!PRESETn)
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if(!PRESETn)
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