| Line 3... |
Line 3... |
////
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////
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//// AES CORE BLOCK
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//// AES CORE BLOCK
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////
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////
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////
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////
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////
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////
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//// This file is part of the APB to AES128 project
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//// This file is part of the APB to I2C project
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////
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////
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//// http://www.opencores.org/cores/apbtoaes128/
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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////
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////
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////
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//// Description
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//// Description
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////
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////
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| Line 94... |
Line 94... |
output dma_req_rd,
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output dma_req_rd,
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output reg start_core,
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output reg start_core,
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output [31:0] PRDATA,
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output [31:0] PRDATA,
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//INPUTS
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//INPUTS
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input [3:0] PADDR,
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input [3:0] PADDR,
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input [31:0] PWDATA,
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input [12:0] PWDATA,
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input PWRITE,
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input PWRITE,
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input PENABLE,
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input PENABLE,
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input PSEL,
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input PSEL,
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input PCLK,
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input PCLK,
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input PRESETn,
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input PRESETn,
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| Line 160... |
Line 160... |
localparam INPUT = 3'd1;
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localparam INPUT = 3'd1;
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localparam START = 3'd2;
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localparam START = 3'd2;
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localparam WAIT = 3'd3;
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localparam WAIT = 3'd3;
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localparam OUTPUT = 3'd4;
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localparam OUTPUT = 3'd4;
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reg [31:0] bus_out;
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wire [31:0] bus_out;
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reg [31:0] bus_out_mux;
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reg [31:0] bus_out_mux;
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reg cnt_en;
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reg cnt_en;
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reg enable_clear;
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reg enable_clear;
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reg access_permission;
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reg access_permission;
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reg first_block_set;
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reg first_block_set;
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| Line 178... |
Line 178... |
wire err_ie;
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wire err_ie;
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wire ccf_ie;
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wire ccf_ie;
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wire errc;
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wire errc;
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wire ccfc;
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wire ccfc;
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wire aes_cr_wr_en;
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wire aes_cr_wr_en;
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//wire aes_sr_wr_en;
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wire wr_err_en;
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wire wr_err_en;
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wire rd_err_en;
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wire rd_err_en;
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wire write_completed;
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wire write_completed;
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wire read_completed;
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wire read_completed;
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wire key_deriv;
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wire key_deriv;
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| Line 192... |
Line 193... |
reg rd_err;
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reg rd_err;
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reg ccf;
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reg ccf;
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reg [2:0] state, next_state;
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reg [2:0] state, next_state;
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reg [1:0] cnt;
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reg [1:0] cnt;
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reg dma_req;
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reg dma_req;
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wire enable;
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// Write and read enable signals
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// Write and read enable signals
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assign write_en = PSEL & PENABLE & PWRITE;
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assign write_en = PSEL & PENABLE & PWRITE;
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assign read_en = PSEL & ~PWRITE;
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assign read_en = (PSEL & ~PWRITE & (ccf_set | ccf))?1'b1:
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((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3 ))?1'b1:1'b0;
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// Configuration Register Logic
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// Configuration Register Logic
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assign dma_out_en = aes_cr[10];
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assign dma_out_en = aes_cr[10];
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assign dma_in_en = aes_cr[9];
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assign dma_in_en = aes_cr[9];
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assign err_ie = aes_cr[8];
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assign err_ie = aes_cr[8];
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| Line 216... |
Line 219... |
assign chmod_in = PWDATA[6:5];
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assign chmod_in = PWDATA[6:5];
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always @(posedge PCLK, negedge PRESETn)
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always @(posedge PCLK, negedge PRESETn)
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begin
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begin
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if(!PRESETn)
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if(!PRESETn)
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aes_cr <= AES_CR_RESET;
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aes_cr <= AES_CR_RESET[10:0];
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else
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else
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begin
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begin
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if(enable_clear)
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if(enable_clear)
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aes_cr[0] <= 1'b0;
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aes_cr[0] <= 1'b0;
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else
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else
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| Line 239... |
Line 242... |
end
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end
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end
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end
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end
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end
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// Status Register Logic
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// Status Register Logic
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assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
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//assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
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always @(posedge PCLK, negedge PRESETn)
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always @(posedge PCLK, negedge PRESETn)
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begin
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begin
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if(!PRESETn)
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if(!PRESETn)
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begin
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{wr_err, rd_err, ccf} <= AES_SR_RESET;
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{wr_err, rd_err, ccf} <= AES_SR_RESET;
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end
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else
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else
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begin
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begin
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// Write Error Flag
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// Write Error Flag
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if(wr_err_en)
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if(wr_err_en)
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wr_err <= 1'b1;
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wr_err <= 1'b1;
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| Line 402... |
Line 408... |
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// DMA Requests Logic
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// DMA Requests Logic
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always @(posedge PCLK, negedge PRESETn)
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always @(posedge PCLK, negedge PRESETn)
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begin
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begin
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if(!PRESETn)
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if(!PRESETn)
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dma_req <= 0;
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dma_req <= 1'b0;
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else
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else
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dma_req <= cnt[0];
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dma_req <= cnt[0];
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end
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end
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assign dma_req_wr = (dma_req ^ cnt[0]) & dma_in_en & enable & (state == INPUT || state == IDLE);
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assign dma_req_wr = (dma_req ^ cnt[0]) & dma_in_en & enable & (state == INPUT || state == IDLE);
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| Line 421... |
Line 427... |
bus_out_mux = 32'd0;
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bus_out_mux = 32'd0;
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case(PADDR)
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case(PADDR)
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AES_CR:
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AES_CR:
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bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
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bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
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AES_SR:
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AES_SR:
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, ccf};
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begin
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
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/*
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if(~ccfc && ~aes_cr_wr_en)
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begin
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
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end
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else
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begin
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bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set | ccf)?1'b1:1'b0};
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end
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*/
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end
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AES_DINR, AES_DOUTR:
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AES_DINR, AES_DOUTR:
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bus_out_mux = col_bus;
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bus_out_mux = col_bus;
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AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
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AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
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if(!enable)
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bus_out_mux = key_bus;
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bus_out_mux = key_bus;
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AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
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AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
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if(!enable)
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if(!enable)
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bus_out_mux = iv_bus;
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bus_out_mux = iv_bus;
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endcase
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endcase
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end
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end
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// The output Bus is registered
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// The output Bus is registered
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always @(posedge PCLK, negedge PRESETn)
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begin
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assign bus_out =(read_en)? bus_out_mux:32'd0;
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if(!PRESETn)
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bus_out <= 32'd0;
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/*
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else
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always @(posedge PCLK, negedge PRESETn)
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if(read_en)
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begin
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bus_out <= bus_out_mux;
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if(!PRESETn)
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end
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bus_out <= 32'd0;
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else
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if(read_en)
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bus_out <= bus_out_mux;
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end
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*/
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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