| Line 95... |
Line 95... |
// State Matrix generation
|
// State Matrix generation
|
//=====================================================================================
|
//=====================================================================================
|
generate
|
generate
|
genvar l,c;
|
genvar l,c;
|
for(l = 0; l < ST_LINE; l = l + 1)
|
for(l = 0; l < ST_LINE; l = l + 1)
|
|
begin:SMG
|
for(c = 0; c < ST_COL; c = c + 1)
|
for(c = 0; c < ST_COL; c = c + 1)
|
|
begin:BLOCK
|
assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
|
assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
|
|
end
|
|
end
|
endgenerate
|
endgenerate
|
|
|
//=====================================================================================
|
//=====================================================================================
|
// Shift Row operation
|
// Shift Row operation
|
//=====================================================================================
|
//=====================================================================================
|
generate
|
generate
|
genvar l1,c1;
|
genvar l1,c1;
|
for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
|
for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
|
|
begin:SRO
|
for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
|
for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
|
begin
|
begin:BLOCK
|
assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
|
assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
|
assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
|
assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
|
end
|
end
|
|
end
|
endgenerate
|
endgenerate
|
|
|
//=====================================================================================
|
//=====================================================================================
|
// State Matrix to Bus Output Transformation
|
// State Matrix to Bus Output Transformation
|
//=====================================================================================
|
//=====================================================================================
|
generate
|
generate
|
genvar l2,c2;
|
genvar l2,c2;
|
for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
|
for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
|
|
begin:SMBOT
|
for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
|
for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
|
begin
|
begin:BLOCK
|
assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
|
assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
|
assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
|
assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
|
end
|
end
|
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
