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// State Matrix generation
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// State Matrix generation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l,c;
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genvar l,c;
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for(l = 0; l < ST_LINE; l = l + 1)
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for(l = 0; l < ST_LINE; l = l + 1)
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begin:SMG
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for(c = 0; c < ST_COL; c = c + 1)
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for(c = 0; c < ST_COL; c = c + 1)
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begin:BLOCK
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assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
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assign state[l][c] = data_in[ST_WORD*((ST_COL - c)*ST_LINE - l) - 1 : ST_WORD*((ST_COL - c)*ST_LINE - l - 1)];
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end
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end
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endgenerate
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endgenerate
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//=====================================================================================
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//=====================================================================================
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// Shift Row operation
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// Shift Row operation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l1,c1;
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genvar l1,c1;
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for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
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for(l1 = 0; l1 < ST_LINE; l1 = l1 + 1)
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begin:SRO
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for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
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for(c1 = 0; c1 < ST_COL; c1 = c1 + 1)
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begin
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begin:BLOCK
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assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
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assign state_sft_l[l1][c1] = state[l1][(c1 + l1)%ST_COL];
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assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
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assign state_sft_r[l1][c1] = state[l1][(c1 + (ST_COL - l1))%ST_COL];
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end
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end
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end
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endgenerate
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endgenerate
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//=====================================================================================
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//=====================================================================================
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// State Matrix to Bus Output Transformation
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// State Matrix to Bus Output Transformation
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//=====================================================================================
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//=====================================================================================
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generate
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generate
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genvar l2,c2;
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genvar l2,c2;
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for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
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for(l2 = 0; l2 < ST_LINE; l2 = l2 + 1)
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begin:SMBOT
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for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
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for(c2 = 0; c2 < ST_COL; c2 = c2 + 1)
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begin
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begin:BLOCK
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assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
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assign data_out_enc[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_l[l2][c2];
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assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
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assign data_out_dec[ST_WORD*((ST_COL - c2)*ST_LINE - l2) - 1 : ST_WORD*((ST_COL - c2)*ST_LINE - l2 - 1)] = state_sft_r[l2][c2];
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end
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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