URL
https://opencores.org/ocsvn/apbtoaes128/apbtoaes128/trunk
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| Rev 6 |
Rev 12 |
| Line 115... |
Line 115... |
.int_err(int_err),
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.int_err(int_err),
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.dma_req_wr(dma_req_wr),
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.dma_req_wr(dma_req_wr),
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.dma_req_rd(dma_req_rd)
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.dma_req_rd(dma_req_rd)
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);
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);
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integer i;
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integer i,a;
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initial
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initial
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begin
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begin
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$dumpfile("AES_GLADIC_tb.vcd");
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$dumpfile("AES_GLADIC_tb.vcd");
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$dumpvars(0,AES_GLADIC_tb);
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$dumpvars(0,AES_GLADIC_tb);
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| Line 249... |
Line 249... |
$bfm_derivation_decryption_dma_cbc_aes128;
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$bfm_derivation_decryption_dma_cbc_aes128;
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always@(posedge PCLK)
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always@(posedge PCLK)
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$bfm_derivation_decryption_ccfie_cbc_aes128;
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$bfm_derivation_decryption_ccfie_cbc_aes128;
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//
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//SUFLE
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always@(posedge PCLK)
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$bfm_sufle_aes128;
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//WRITE READ REGISTERS
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always@(posedge PCLK)
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always@(posedge PCLK)
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$bfm_wr_aes128;
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$bfm_wr_aes128;
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//TRY TO WRITE ON DINR WHILE CR[0] EQUAL 1
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always@(posedge PCLK)
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always@(posedge PCLK)
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$bfm_wr_error_dinr_aes128;
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$bfm_wr_error_dinr_aes128;
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//TRY TO READ/WRITE ON DOUTR/DINR WHILE CR[0] EQUAL 1
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always@(posedge PCLK)
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always@(posedge PCLK)
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$bfm_wr_error_doutr_aes128;
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$bfm_wr_error_doutr_aes128;
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//
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//CHOOSE WHAT BFM WILL BE ENABLED
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always@(posedge PCLK)
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always@(posedge PCLK)
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$bfm_generate_type;
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$bfm_generate_type;
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//
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//RESET DUT A FEW TIMES TO GO TO RIGHT STATE
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always@(posedge PCLK)
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always@(posedge PCLK)
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$reset_aes128;
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$reset_aes128;
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//
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//THIS CATCH INFORMATION FROM INPUT and CHECK IT
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always@(posedge PCLK)
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always@(posedge PCLK)
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begin
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$monitor_aes;
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$monitor_aes;
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@(posedge PENABLE);
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end
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//
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//THIS MAKE REGISTER INITIAL ASSIGNMENT
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always@(negedge PRESETn)
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always@(negedge PRESETn)
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$init;
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$init;
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//FLAG USED TO FINISH SIMULATION PROGRAM
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always@(posedge PCLK)
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always@(posedge PCLK)
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begin
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begin
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while( i != 1)
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begin
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wait(i == 1);
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@(posedge PCLK);
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end
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$finish();
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$finish();
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end
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end
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