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Subversion Repositories apbtoaes128

[/] [apbtoaes128/] [trunk/] [testbench/] [aes_tb_vpi.v] - Diff between revs 6 and 12

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Rev 6 Rev 12
Line 115... Line 115...
                .int_err(int_err),
                .int_err(int_err),
                .dma_req_wr(dma_req_wr),
                .dma_req_wr(dma_req_wr),
                .dma_req_rd(dma_req_rd)
                .dma_req_rd(dma_req_rd)
        );
        );
 
 
        integer i;
        integer i,a;
 
 
        initial
        initial
         begin
         begin
            $dumpfile("AES_GLADIC_tb.vcd");
            $dumpfile("AES_GLADIC_tb.vcd");
            $dumpvars(0,AES_GLADIC_tb);
            $dumpvars(0,AES_GLADIC_tb);
Line 249... Line 249...
                $bfm_derivation_decryption_dma_cbc_aes128;
                $bfm_derivation_decryption_dma_cbc_aes128;
 
 
        always@(posedge PCLK)
        always@(posedge PCLK)
                $bfm_derivation_decryption_ccfie_cbc_aes128;
                $bfm_derivation_decryption_ccfie_cbc_aes128;
 
 
        //
        //SUFLE
 
        always@(posedge PCLK)
 
                $bfm_sufle_aes128;
 
 
 
        //WRITE READ REGISTERS
        always@(posedge PCLK)
        always@(posedge PCLK)
                $bfm_wr_aes128;
                $bfm_wr_aes128;
 
 
 
        //TRY TO WRITE ON DINR WHILE CR[0] EQUAL 1 
        always@(posedge PCLK)
        always@(posedge PCLK)
                $bfm_wr_error_dinr_aes128;
                $bfm_wr_error_dinr_aes128;
 
 
 
        //TRY TO READ/WRITE ON DOUTR/DINR WHILE CR[0] EQUAL 1 
        always@(posedge PCLK)
        always@(posedge PCLK)
                $bfm_wr_error_doutr_aes128;
                $bfm_wr_error_doutr_aes128;
 
 
        //
        //CHOOSE WHAT BFM WILL BE ENABLED
        always@(posedge PCLK)
        always@(posedge PCLK)
                $bfm_generate_type;
                $bfm_generate_type;
 
 
        //
        //RESET DUT A FEW TIMES TO GO TO RIGHT STATE
        always@(posedge PCLK)
        always@(posedge PCLK)
                $reset_aes128;
                $reset_aes128;
 
 
        //
        //THIS CATCH INFORMATION FROM INPUT and CHECK IT 
        always@(posedge PCLK)
        always@(posedge PCLK)
 
        begin
                $monitor_aes;
                $monitor_aes;
 
                @(posedge PENABLE);
 
        end
 
 
        //
        //THIS MAKE REGISTER INITIAL ASSIGNMENT
        always@(negedge PRESETn)
        always@(negedge PRESETn)
                $init;
                $init;
 
 
 
        //FLAG USED TO FINISH SIMULATION PROGRAM 
        always@(posedge PCLK)
        always@(posedge PCLK)
        begin
        begin
                while( i != 1)
 
                begin
                wait(i == 1);
                        @(posedge PCLK);
 
                end
 
                $finish();
                $finish();
        end
        end
 
 
 
 
 
 

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