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https://opencores.org/ocsvn/artec_dongle_ii_fpga/artec_dongle_ii_fpga/trunk
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signal data_lo_seg1 : std_logic_vector(7 downto 0);
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signal data_lo_seg1 : std_logic_vector(7 downto 0);
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signal data_hi_seg0 : std_logic_vector(7 downto 0);
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signal data_hi_seg0 : std_logic_vector(7 downto 0);
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signal data_lo_seg0 : std_logic_vector(7 downto 0);
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signal data_lo_seg0 : std_logic_vector(7 downto 0);
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--constant display
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--constant display
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signal cons_hi_seg1 : std_logic_vector(7 downto 0);
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--signal cons_hi_seg1 : std_logic_vector(7 downto 0);
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signal cons_lo_seg1 : std_logic_vector(7 downto 0);
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--signal cons_lo_seg1 : std_logic_vector(7 downto 0);
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signal cons_hi_seg0 : std_logic_vector(7 downto 0);
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--signal cons_hi_seg0 : std_logic_vector(7 downto 0);
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signal cons_lo_seg0 : std_logic_vector(7 downto 0);
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--signal cons_lo_seg0 : std_logic_vector(7 downto 0);
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signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
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signal disp_cnt : std_logic_vector(15 downto 0):=(others=>'0'); --this enables correct simulation
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begin -- rtl
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begin -- rtl
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---------------------------HGFEDCBA
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cons_hi_seg1 <= msn_hib;--"01111111"; --8
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cons_lo_seg1 <= lsn_hib;--"01111101"; --6
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cons_hi_seg0 <= msn_lob;--"01011100"; -- small o
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cons_lo_seg0 <= lsn_lob;--"01011100"; -- small o
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process (clk) --enable the scanning while in reset
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process (clk) --enable the scanning while in reset
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begin -- process
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begin -- process
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if clk'event and clk = '0' then -- rising clock edge
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if clk'event and clk = '0' then -- rising clock edge
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disp_cnt <= disp_cnt + 1;
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disp_cnt <= disp_cnt + 1;
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