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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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entity lpc_iow is
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entity lpc_iow is
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port (
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port (
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--system signals
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--system signals
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lreset_n : in std_logic;
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lreset_n : in std_logic;
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lclk : in std_logic;
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lclk : in std_logic;
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lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
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lena_reads : in std_logic; --enable read capabilities
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lena_reads : in std_logic; --enable read capabilities
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uart_addr : in std_logic_vector(15 downto 0); -- define UART address to listen to
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--LPC bus from host
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--LPC bus from host
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lad_i : in std_logic_vector(3 downto 0);
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lad_i : in std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_o : out std_logic_vector(3 downto 0);
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lad_oe : out std_logic;
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lad_oe : out std_logic;
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lframe_n : in std_logic;
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lframe_n : in std_logic;
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--memory interface
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--memory interface
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_addr : out std_logic_vector(23 downto 0); --shared address
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lpc_wr : out std_logic; --shared write not read
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lpc_wr : out std_logic; --shared write not read
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lpc_io : out std_logic; --io access not mem access select
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lpc_uart : out std_logic; --uart mapped cycle coming
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lpc_gpioled: out std_logic; --gpio led cycle coming
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_i : in std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_data_o : out std_logic_vector(7 downto 0);
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lpc_val : out std_logic;
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lpc_val : out std_logic;
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lpc_ack : in std_logic
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lpc_ack : in std_logic
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);
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);
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end lpc_iow;
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end lpc_iow;
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architecture rtl of lpc_iow is
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architecture rtl of lpc_iow is
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type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
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type state is (RESETs,STARTs,ADDRs,TARs,SYNCs,DATAs,LOCAL_TARs); -- simple LCP states
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type cycle is (LPC_IO_W,LPC_MEM_R,LPC_FW_R); -- simple LPC bus cycle types
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type cycle is (LPC_IO_W, LPC_IO_R, LPC_MEM_R, LPC_FW_R); -- simple LPC bus cycle types
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signal CS : state;
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signal CS : state;
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signal r_lad : std_logic_vector(3 downto 0);
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signal r_lad : std_logic_vector(3 downto 0);
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signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
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signal r_addr : std_logic_vector(31 downto 0); --should consider saving max
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--adress 23 bits on flash
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--adress 23 bits on flash
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| Line 77... |
Line 80... |
constant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the bus
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constant SYNC_WAIT : std_logic_vector(3 downto 0):="0101"; --sync wait device holds the bus
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constant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the bus
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constant SYNC_LWAIT : std_logic_vector(3 downto 0):="0110"; --sync long wait expected device holds the bus
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constant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave
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constant TAR_OK : std_logic_vector(3 downto 0):="1111"; --accepted tar constant for master and slave
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begin -- rtl
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begin -- rtl
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lad_o<= lad_rising_o;
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lad_o<= lad_rising_o;
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lad_oe <= lad_rising_oe;
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lad_oe <= lad_rising_oe;
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--Pass the whole LPC address to the system
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--Pass the whole LPC address to the system
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lpc_addr <= r_addr(23 downto 0);
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lpc_addr <= r_addr(23 downto 0);
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lpc_data_o<= r_data;
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lpc_data_o<= r_data;
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-- purpose: LPC IO write/LPC MEM read/LPC FW read handler
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-- purpose: LPC IO write/LPC MEM read/LPC FW read handler
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-- type : sequential
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-- type : sequential
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-- inputs : lclk, lreset_n
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-- inputs : lclk, lreset_n
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-- outputs:
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-- outputs:
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LPC: process (lclk, lreset_n)
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LPC: process (lclk, lreset_n)
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Line 101... |
CS<= RESETs;
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CS<= RESETs;
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lad_rising_oe<='0';
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lad_rising_oe<='0';
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data_valid <='1';
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data_valid <='1';
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lad_rising_o<="0000";
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lad_rising_o<="0000";
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lpc_val <='0';
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lpc_val <='0';
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lpc_uart <= '0';
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lpc_gpioled <= '0';
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lpc_io <= '0';
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lpc_wr <='0';
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lpc_wr <='0';
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r_lad <= (others=>'0');
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r_lad <= (others=>'0');
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cycle_type <= LPC_IO_W; --initial value
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cycle_type <= LPC_IO_W; --initial value
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r_addr <= (others=>'0');
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r_addr <= (others=>'0');
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r_cnt <= (others=>'0');
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r_cnt <= (others=>'0');
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elsif lclk'event and lclk = '1' then -- rising clock edge
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elsif lclk'event and lclk = '1' then -- rising clock edge
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case CS is
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case CS is
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when RESETs => ----------------------------------------------------------
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when RESETs => ----------------------------------------------------------
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lpc_wr <='0';
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lpc_wr <='0';
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lpc_val <='0';
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lpc_val <='0';
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lpc_uart<= '0';
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lpc_gpioled<= '0';
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r_addr<=(others => '0');
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lpc_io<='0';
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if lframe_n='0' then
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if lframe_n='0' then
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CS <= STARTs;
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CS <= STARTs;
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r_lad <= lad_i;
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r_lad <= lad_i;
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else
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else
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CS <= RESETs;
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CS <= RESETs;
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--must identify CYCTYPE
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--must identify CYCTYPE
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if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
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if lad_i(3 downto 1)="001" then --IO WRITE WILL HAPPEN
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--next 4 states must be address states
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--next 4 states must be address states
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CS<=ADDRs;
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CS<=ADDRs;
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cycle_type <= LPC_IO_W;
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cycle_type <= LPC_IO_W;
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lpc_io<='1';
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r_cnt <= "000";
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elsif lad_i(3 downto 1) = "000" then --IO READ WILL HAPPEN
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--next 4 states must be address states
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CS <= ADDRs;
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cycle_type <= LPC_IO_R;
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lpc_io<='1';
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r_cnt <= "000";
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r_cnt <= "000";
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elsif lad_i(3 downto 1)="010" and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
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elsif lad_i(3 downto 1)="010" and lena_mem_r='1' and lena_reads='1' then --MEM READ ALLOWED
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CS<=ADDRs;
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CS<=ADDRs;
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cycle_type <= LPC_MEM_R;
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cycle_type <= LPC_MEM_R;
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lpc_io<='0';
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r_cnt <= "000";
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r_cnt <= "000";
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else
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else
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CS<= RESETs;
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CS<= RESETs;
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end if;
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end if;
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elsif r_lad = START_FW_READ then --FW READ is always allowed
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elsif r_lad = START_FW_READ then --FW READ is always allowed
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if lad_i = IDSEL_FW_BOOT and lena_reads='1' then
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if lad_i = IDSEL_FW_BOOT and lena_reads='1' then
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lpc_io<='0';
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CS<=ADDRs;
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CS<=ADDRs;
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cycle_type <= LPC_FW_R;
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cycle_type <= LPC_FW_R;
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r_cnt <= "000";
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r_cnt <= "000";
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else
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else
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CS<= RESETs;
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CS<= RESETs;
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end if;
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end if;
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end if;
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end if;
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when ADDRs => -----------------------------------------------------------
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when ADDRs => -----------------------------------------------------------
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case cycle_type is
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case cycle_type is
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when LPC_IO_W => --IO write cycle
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when LPC_IO_W | LPC_IO_R => --IO write cycle or IO read cycle
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if r_cnt ="011" then
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if r_cnt ="011" then
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if r_addr(11 downto 0)=x"008" and lad_i(3 downto 2)="00" then
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if r_addr(11 downto 0) = x"008" and lad_i(3 downto 2) = "00" and cycle_type=LPC_IO_W then
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r_addr<= r_addr(27 downto 0)&lad_i;
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r_cnt <= "000";
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CS<=DATAs;
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CS<=DATAs;
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elsif r_addr(11 downto 0)=x"008" and lad_i(3 downto 0)=x"8" then --for debug switch
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elsif r_addr(11 downto 0) = x"008" and lad_i(3 downto 0) = x"4" then --LED and jumpers
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r_addr<= r_addr(27 downto 0)&lad_i;
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lpc_gpioled<='1'; --must decode
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if cycle_type=LPC_IO_W then
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CS <= DATAs;
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else
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r_cnt <= "000";
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r_cnt <= "000";
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lpc_wr <= '0'; --IO read must accure
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lpc_val <= '1';
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data_valid <= '0';
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CS <= TARs; --on read we must do sync for read over clock grossing
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end if;
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elsif r_addr(11 downto 0) = x"008" and lad_i(3 downto 0) = x"8" and cycle_type=LPC_IO_W then --for debug switch
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CS <= DATAs;
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elsif uart_addr(3)='1' and r_addr(11 downto 0)=uart_addr(15 downto 4) and uart_addr(3)=lad_i(3) then --UART selected and enabled by leagal uart addr
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lpc_uart<='1'; --decoded an uart cycle
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if cycle_type=LPC_IO_W then
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CS<=DATAs;
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CS<=DATAs;
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else
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else
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r_cnt <= "000";
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lpc_wr <= '0'; --IO read must accure
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lpc_val <= '1';
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data_valid <= '0';
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CS <= TARs; --on read we must do sync for read over clock grossing
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end if;
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else
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--not for this device
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--not for this device
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CS<=RESETs;
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CS<=RESETs;
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end if;
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end if;
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r_addr <= r_addr(27 downto 0) & lad_i;
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r_cnt <= "000";
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else
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else
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r_addr<= r_addr(27 downto 0)&lad_i;
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r_addr<= r_addr(27 downto 0)&lad_i;
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r_cnt<=r_cnt + 1;
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r_cnt<=r_cnt + 1;
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CS<=ADDRs;
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CS<=ADDRs;
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end if;
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end if;
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Line 249... |
else
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else
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r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
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r_data <= lad_i&r_data(7 downto 4); --LSB first from io cycle
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r_cnt<=r_cnt + 1;
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r_cnt<=r_cnt + 1;
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CS <= DATAs;
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CS <= DATAs;
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end if;
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end if;
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when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
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when LPC_MEM_R | LPC_FW_R | LPC_IO_R => --Memory/FW/IO read cycle
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if r_cnt ="001" then
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if r_cnt ="001" then
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lad_rising_o<= r_data(7 downto 4);
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lad_rising_o<= r_data(7 downto 4);
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r_cnt <= "000";
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r_cnt <= "000";
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CS <= LOCAL_TARs;
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CS <= LOCAL_TARs;
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else
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else
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Line 294... |
case cycle_type is
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case cycle_type is
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when LPC_IO_W => --IO write cycle
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when LPC_IO_W => --IO write cycle
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-- just passing r_lad on bus again
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-- just passing r_lad on bus again
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lad_rising_o<= TAR_OK;
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lad_rising_o<= TAR_OK;
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CS <= LOCAL_TARs;
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CS <= LOCAL_TARs;
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when LPC_MEM_R | LPC_FW_R => --Memory/FW read cycle
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when LPC_MEM_R | LPC_FW_R | LPC_IO_R => --Memory/FW/IO read cycle
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if data_valid ='1' then
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if data_valid ='1' then
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lad_rising_o<=SYNC_OK;
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lad_rising_o<=SYNC_OK;
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CS <= DATAs;
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CS <= DATAs;
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else
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else
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if lpc_ack='1' then
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if lpc_ack='1' then
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| Line 283... |
Line 315... |
case cycle_type is
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case cycle_type is
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when LPC_IO_W => --IO write cycle
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when LPC_IO_W => --IO write cycle
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lpc_wr <='0';
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lpc_wr <='0';
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lad_rising_oe <='0';
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lad_rising_oe <='0';
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CS <= RESETs;
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CS <= RESETs;
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when LPC_MEM_R | LPC_FW_R => --Memory read cycle
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when LPC_MEM_R | LPC_FW_R | LPC_IO_R => -- read cycle
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if r_cnt ="000" then
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if r_cnt ="000" then
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lad_rising_o<= TAR_OK;
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lad_rising_o<= TAR_OK;
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r_cnt <= r_cnt + 1;
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r_cnt <= r_cnt + 1;
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else
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else
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lad_rising_oe <= '0';
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lad_rising_oe <= '0';
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