| Line 20... |
Line 20... |
--
|
--
|
-- The complete text of the GNU Lesser General Public License can be found in
|
-- The complete text of the GNU Lesser General Public License can be found in
|
-- the file 'lesser.txt'.
|
-- the file 'lesser.txt'.
|
|
|
|
|
|
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
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-- Company: ArtecDesign
|
-- Company: ArtecDesign
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-- Engineer: Jüri Toomessoo
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-- Engineer: Jüri Toomessoo
|
--
|
--
|
-- Create Date: 12:57:23 28/02/2008
|
-- Create Date: 12:57:23 28/02/2008
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| Line 64... |
Line 63... |
dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
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dbg_usedw : out STD_LOGIC_VECTOR (12 DOWNTO 0);
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--debug USB port
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--debug USB port
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dbg_usb_mode_en: in std_logic; -- enable this debug mode
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dbg_usb_mode_en: in std_logic; -- enable this debug mode
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_wr : out std_logic; -- write performed on edge \ of signal
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_txe_n : in std_logic; -- tx fifo not full (redy for new data if low)
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dbg_usb_bd : inout std_logic_vector(7 downto 0) --bus data
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dbg_usb_bd : out std_logic_vector(7 downto 0) --bus data
|
);
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);
|
|
|
end pc_serializer;
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end pc_serializer;
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|
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architecture rtl of pc_serializer is
|
architecture rtl of pc_serializer is
|
|
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component fifo
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component fifo
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PORT
|
PORT(
|
(
|
|
aclr : IN STD_LOGIC ;
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aclr : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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clock : IN STD_LOGIC ;
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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rdreq : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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almost_full : OUT STD_LOGIC ;
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almost_full : OUT STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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empty : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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full : OUT STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
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usedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0)
|
|
|
);
|
);
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end component;
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end component;
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|
|
|
|
|
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--type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
|
--type state is (RESETs, HEXMARKs,MSNIBBLEs,LSNIBBLEs,LINEFDs,CRs,START_WRITEs,END_WRITEs,WAITs); -- simple ASCII converter to USB fifo
|
signal CS : std_logic_vector(8 downto 0);--state;
|
signal CS : std_logic_vector(8 downto 0);--state;
|
signal RETS : std_logic_vector(8 downto 0); --state;
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signal RETS : std_logic_vector(8 downto 0); --state;
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signal next_char : std_logic_vector(7 downto 0); --bus data
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signal next_char : std_logic_vector(7 downto 0); --bus data
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signal ascii_char : std_logic_vector(7 downto 0); --bus data
|
signal ascii_char : std_logic_vector(7 downto 0); --bus data
|
| Line 102... |
Line 96... |
|
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signal count : std_logic_vector(3 downto 0); --internal counter
|
signal count : std_logic_vector(3 downto 0); --internal counter
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signal dly_count : std_logic_vector(15 downto 0); --internal counter
|
signal dly_count : std_logic_vector(15 downto 0); --internal counter
|
signal dbg_wr_pulse : std_logic; --active reset
|
signal dbg_wr_pulse : std_logic; --active reset
|
signal dbg_wrd : std_logic; --active reset
|
signal dbg_wrd : std_logic; --active reset
|
signal dbg_wr_len : std_logic; --active reset
|
--signal dbg_wr_len : std_logic; --active reset
|
signal usb_send : std_logic; --active reset
|
signal usb_send : std_logic; --active reset
|
|
|
|
|
signal rdreq_sig : std_logic; --active reset
|
signal rdreq_sig : std_logic; --active reset
|
signal empty_sig : std_logic; --active reset
|
signal empty_sig : std_logic; --active reset
|
| Line 151... |
Line 145... |
constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
|
constant CHAR_c : std_logic_vector(7 downto 0):= x"43";
|
constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
|
constant CHAR_d : std_logic_vector(7 downto 0):= x"44";
|
constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
|
constant CHAR_e : std_logic_vector(7 downto 0):= x"45";
|
constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
|
constant CHAR_f : std_logic_vector(7 downto 0):= x"46";
|
|
|
|
|
|
|
begin
|
begin
|
|
|
ascii_char <=CHAR_0 when in_nibble = x"0" else
|
ascii_char <=CHAR_0 when in_nibble = x"0" else
|
CHAR_1 when in_nibble = x"1" else
|
CHAR_1 when in_nibble = x"1" else
|
CHAR_2 when in_nibble = x"2" else
|
CHAR_2 when in_nibble = x"2" else
|
CHAR_3 when in_nibble = x"3" else
|
CHAR_3 when in_nibble = x"3" else
|
CHAR_4 when in_nibble = x"4" else
|
CHAR_4 when in_nibble = x"4" else
|
| Line 172... |
Line 163... |
CHAR_c when in_nibble = x"c" else
|
CHAR_c when in_nibble = x"c" else
|
CHAR_d when in_nibble = x"d" else
|
CHAR_d when in_nibble = x"d" else
|
CHAR_e when in_nibble = x"e" else
|
CHAR_e when in_nibble = x"e" else
|
CHAR_f when in_nibble = x"f";
|
CHAR_f when in_nibble = x"f";
|
|
|
|
dbg_usb_bd <= usb_send_char;
|
|
|
|
dbg_usb_wr <= usb_send;
|
dbg_usb_bd <= usb_send_char when dbg_usb_mode_en = '1' else
|
|
(others=>'Z');
|
|
|
|
dbg_usb_wr <= usb_send when dbg_usb_mode_en = '1' else
|
|
'Z';
|
|
|
|
SER_SM: process (sys_clk,resetn)
|
SER_SM: process (sys_clk,resetn)
|
begin -- process
|
begin -- process
|
|
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
| Line 279... |
Line 266... |
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SER_SM;
|
end process SER_SM;
|
|
|
|
|
SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
|
SYNCER: process (sys_clk,resetn) --make slower clock and 2 cycle write pulse
|
begin -- process
|
begin -- process
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if sys_clk'event and sys_clk = '1' then -- rising clock edge
|
if resetn='0' then --active low reset
|
if resetn='0' then --active low reset
|
dbg_wr_pulse <='0';
|
dbg_wr_pulse <='0';
|
dbg_wr_len <='0';
|
--dbg_wr_len <= '0';
|
dbg_wrd <='0';
|
dbg_wrd <='0';
|
else
|
else
|
dbg_wrd <= dbg_wr;
|
dbg_wrd <= dbg_wr;
|
if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
|
if dbg_wrd='0' and dbg_wr='1' then -- rising front on fifo write
|
dbg_wr_pulse <='1';
|
dbg_wr_pulse <='1';
|
| Line 298... |
Line 284... |
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process SYNCER;
|
end process SYNCER;
|
|
|
|
|
reset <= not resetn;
|
reset <= not resetn;
|
dbg_full <= full_sig;
|
dbg_full <= full_sig;
|
dbg_almost_full<= almost_full;
|
dbg_almost_full<= almost_full;
|
fifo_inst : fifo PORT MAP (
|
fifo_inst : fifo PORT MAP (
|
--system signals
|
--system signals
|
| Line 318... |
Line 303... |
empty => empty_sig,
|
empty => empty_sig,
|
full => full_sig,
|
full => full_sig,
|
q => q_sig
|
q => q_sig
|
);
|
);
|
|
|
|
|
|
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
