| Line 74... |
Line 74... |
usb_mode_en: in std_logic; -- enable this block
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usb_mode_en: in std_logic; -- enable this block
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_rd_n : out std_logic; -- enables out data if low (next byte detected by edge / in usb chip)
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_wr : out std_logic; -- write performed on edge \ of signal
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_txe_n : in std_logic; -- tx fifo empty (redy for new data if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_rxf_n : in std_logic; -- rx fifo empty (data redy if low)
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usb_bd : inout std_logic_vector(7 downto 0) --bus data
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usb_bd_o : out std_logic_vector(7 downto 0); --bus data
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usb_bd : in std_logic_vector(7 downto 0) --bus data
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);
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);
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end usb2mem;
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end usb2mem;
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|
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architecture RTL of usb2mem is
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architecture RTL of usb2mem is
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| Line 99... |
Line 100... |
signal cmd_cnt : std_logic_vector(15 downto 0);
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signal cmd_cnt : std_logic_vector(15 downto 0);
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signal state_cnt : std_logic_vector(3 downto 0);
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signal state_cnt : std_logic_vector(3 downto 0);
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--shyncro to USB
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--shyncro to USB
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signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
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signal usb_txe_nd : std_logic; -- tx fifo empty (redy for new data if low)
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signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
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signal usb_rxf_nd : std_logic; -- rx fifo empty (data redy if low)
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signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
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--signal internal_cmd : std_logic; -- rx fifo empty (data redy if low)
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|
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signal read_mode : std_logic;
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signal read_mode : std_logic;
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signal write_mode : std_logic;
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--signal write_mode : std_logic;
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signal write_count : std_logic;
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signal write_count : std_logic;
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signal first_word : std_logic;
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signal first_word : std_logic;
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signal mem_busy_nd : std_logic;
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signal mem_busy_nd : std_logic;
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begin
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begin
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--define internal command codes
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usb_wr <= usb_wr_d;
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internal_cmd <='1' when data_reg_i(7 downto 0) = x"C5" else
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'1' when data_reg_i(7 downto 0) = x"CD" else
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'1' when data_reg_i(7 downto 0) = x"A0" else
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'1' when data_reg_i(7 downto 0) = x"A1" else
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'1' when data_reg_i(7 downto 0) = x"A2" else
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'1' when data_reg_i(7 downto 0) = x"3F" else
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--These are spechial attention Flash commands
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'1' when data_reg_i(7 downto 0) = x"E8" else
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'1' when data_reg_i(7 downto 0) = x"E9" else
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'0';
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|
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usb_wr <= usb_wr_d when usb_mode_en='1' else
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'Z';
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-- this goes to byte buffer for that reason send LSB first and MSB second
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-- this goes to byte buffer for that reason send LSB first and MSB second
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usb_bd <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
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usb_bd_o <=data_reg_o(7 downto 0)when data_oe='1' and CS=TXCMD0s and usb_mode_en='1' else --LSB byte first
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data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else --MSB byte second
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data_reg_o(15 downto 8) when data_oe='1' and CS=TXCMD1s and usb_mode_en='1' else
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(others=>'Z');
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(others=>'0');
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process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
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process (clk25,reset_n) --enable the scanning while in reset (simulation will be incorrect)
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begin -- process
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begin -- process
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if reset_n='0' then
|
if reset_n='0' then
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| Line 144... |
Line 130... |
usb_wr_d <= '0';
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usb_wr_d <= '0';
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usb_txe_nd <= '1';
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usb_txe_nd <= '1';
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usb_rxf_nd <= '1';
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usb_rxf_nd <= '1';
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data_oe <='0';
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data_oe <='0';
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state_cnt <=(others=>'0'); --init command counter
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state_cnt <=(others=>'0'); --init command counter
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mem_do <= (others=>'Z');
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mem_do <= (others=>'0');
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mem_addr <= (others=>'Z');
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mem_addr <= (others=>'0');
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addr_reg <= (others=>'0');
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addr_reg <= (others=>'0');
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mem_val <= '0';
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mem_val <= '0';
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mem_wr <='0';
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mem_wr <='0';
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mem_cmd <='0';
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mem_cmd <='0';
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cmd_cnt <= (others=>'0');
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cmd_cnt <= (others=>'0');
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read_mode <='0';
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read_mode <='0';
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write_mode <='0';
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write_count <='0';
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write_count <='0';
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first_word <='0';
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first_word <='0';
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mem_idle <='1'; --set idle
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mem_idle <='1'; --set idle
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mem_busy_nd <='1';
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mem_busy_nd <='1';
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usb_buf_en <='1'; -- default mode (USB prog disabled, buffer with HiZ outputs)
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usb_buf_en <='1'; -- default mode (USB prog disabled, buffer with HiZ outputs)
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