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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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use work.wb_init.all; -- initialization package, comment out when not used
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use work.wb_init.all; -- initialization package, comment out when not used
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-- Deprecated XPS library:
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-- Deprecated XPS library:
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--library proc_common_v3_00_a;
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--library proc_common_v3_00_a;
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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--use proc_common_v3_00_a.proc_common_pkg.all; -- Only for simulation ( pad_power2() )
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entity layerPS_top is
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entity layerPS_top is
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generic
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generic
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(
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(
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WBinit : boolean := false;
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NumN : natural := 64; ------- Number of neurons of the layer
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LNum : natural := 0; ------- layer number (needed for initialization)
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NumIn : natural := 8; ------- Number of inputs of each neuron
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NumN : natural := 34; ------- Number of neurons of the layer
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NbitIn : natural := 12; ------- Bit width of the input data
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NumIn : natural := 27; ------- Number of inputs of each neuron
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NbitW : natural := 8; ------- Bit width of weights and biases
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitW : natural := 1; ------- Bit width of weights and biases
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NbitOut : natural := 8; ------- Bit width of the output data
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NbitOut : natural := 8; ------- Bit width of the output data
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lra_l : natural := 11; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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lra_l : natural := 10; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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wra_l : natural := 5; ------- Weight RAM address length. It should value log2(NumIn)
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wra_l : natural := 3; ------- Weight RAM address length. It should value log2(NumIn)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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LSbit : natural := 6 ------- Less significant bit of the outputs
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LSbit : natural := 4; ------- Less significant bit of the outputs
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WBinit : boolean := false;
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LNum : natural := 0 ------- layer number (needed for initialization)
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);
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);
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port
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port
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(
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(
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-- Input ports
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-- Input ports
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end layerPS_top;
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end layerPS_top;
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architecture Behavioral of layerPS_top is
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architecture Behavioral of layerPS_top is
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--type ramd_type is array (pad_power2(NumN)-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces -- pad_power2() only for simulation
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--type layer_ram is array (pad_power2(NumIn)-1 downto 0) of ramd_type;
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type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type ramd_type is array (NumN-1 downto 0) of std_logic_vector(NbitW-1 downto 0); -- Optimal: 32 or 64 spaces
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type layer_ram is array (NumIn-1 downto 0) of ramd_type;
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type layer_ram is array (NumIn-1 downto 0) of ramd_type;
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type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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type outm_type is array (NumIn-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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function fw_init(LNum : natural) return layer_ram is
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function fw_init(LNum : natural) return layer_ram is
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