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[/] [astron_fifo/] [trunk/] [tech_fifo_component_pkg.vhd] - Diff between revs 3 and 4

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Line 18... Line 18... 
--
 
--
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
 
 
 
 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
 
 
 
 
 
LIBRARY IEEE, technology_lib;
 
LIBRARY ieee, common_pkg_lib;
 
USE IEEE.STD_LOGIC_1164.ALL;
 
USE IEEE.STD_LOGIC_1164.ALL;
 
USE technology_lib.technology_pkg.ALL;
 
--USE technology_lib.technology_pkg.ALL;
 
 
 
USE common_pkg_lib.common_pkg.ALL;
 
 
 
 
 
PACKAGE tech_fifo_component_pkg IS
 
PACKAGE tech_fifo_component_pkg IS
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- ip_stratixiv
 
  -- ip_stratixiv
Line 43... Line 44... 
    rdreq : IN STD_LOGIC;
 
    rdreq : IN STD_LOGIC;
 
    wrreq : IN STD_LOGIC;
 
    wrreq : IN STD_LOGIC;
 
    empty : OUT STD_LOGIC;
 
    empty : OUT STD_LOGIC;
 
    full  : OUT STD_LOGIC;
 
    full  : OUT STD_LOGIC;
 
    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
    usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
    usedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
 
 
 
 
  COMPONENT ip_stratixiv_fifo_dc IS
 
  COMPONENT ip_stratixiv_fifo_dc IS
 
  GENERIC (
 
  GENERIC (
Line 61... Line 62... 
    rdreq   : IN STD_LOGIC;
 
    rdreq   : IN STD_LOGIC;
 
    wrclk   : IN STD_LOGIC;
 
    wrclk   : IN STD_LOGIC;
 
    wrreq   : IN STD_LOGIC;
 
    wrreq   : IN STD_LOGIC;
 
    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
    rdempty : OUT STD_LOGIC;
 
    rdempty : OUT STD_LOGIC;
 
    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
 
    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
 
    wrfull  : OUT STD_LOGIC;
 
    wrfull  : OUT STD_LOGIC;
 
    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
 
 
 
 
  COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
 
  COMPONENT ip_stratixiv_fifo_dc_mixed_widths IS
 
  GENERIC (
 
  GENERIC (
Line 82... Line 83... 
    rdreq   : IN STD_LOGIC;
 
    rdreq   : IN STD_LOGIC;
 
    wrclk   : IN STD_LOGIC;
 
    wrclk   : IN STD_LOGIC;
 
    wrreq   : IN STD_LOGIC;
 
    wrreq   : IN STD_LOGIC;
 
    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
    rdempty : OUT STD_LOGIC;
 
    rdempty : OUT STD_LOGIC;
 
    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
    wrfull  : OUT STD_LOGIC;
 
    wrfull  : OUT STD_LOGIC;
 
    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
  );
 
  );
 
  END COMPONENT;
 
  END COMPONENT;
 
 
 
 
 
 
 
 
 
--  -----------------------------------------------------------------------------
 
--  -----------------------------------------------------------------------------
Line 108... Line 109... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--
 
--
 
--  COMPONENT ip_arria10_fifo_dc IS
 
--  COMPONENT ip_arria10_fifo_dc IS
 
--  GENERIC (
 
--  GENERIC (
Line 127... Line 128... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--  
--  
--  COMPONENT ip_arria10_fifo_dc_mixed_widths IS
 
--  COMPONENT ip_arria10_fifo_dc_mixed_widths IS
 
--  GENERIC (
 
--  GENERIC (
Line 148... Line 149... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--
 
--
 
--  -----------------------------------------------------------------------------
 
--  -----------------------------------------------------------------------------
 
--  -- ip_arria10_e3sge3
 
--  -- ip_arria10_e3sge3
Line 173... Line 174... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--
 
--
 
--  COMPONENT ip_arria10_e3sge3_fifo_dc IS
 
--  COMPONENT ip_arria10_e3sge3_fifo_dc IS
 
--  GENERIC (
 
--  GENERIC (
Line 192... Line 193... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--  
--  
--  COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
 
--  COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
 
--  GENERIC (
 
--  GENERIC (
Line 213... Line 214... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--  
--  
--  -----------------------------------------------------------------------------
 
--  -----------------------------------------------------------------------------
 
--  -- ip_arria10_e1sg
 
--  -- ip_arria10_e1sg
Line 238... Line 239... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    empty   : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    full    : OUT STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
 
--    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    usedw   : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--
 
--
 
--  COMPONENT ip_arria10_e1sg_fifo_dc IS
 
--  COMPONENT ip_arria10_e1sg_fifo_dc IS
 
--  GENERIC (
 
--  GENERIC (
Line 257... Line 258... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
--  
--  
--  COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
 
--  COMPONENT ip_arria10_e1sg_fifo_dc_mixed_widths IS
 
--  GENERIC (
 
--  GENERIC (
Line 278... Line 279... 
--    rdreq   : IN STD_LOGIC ;
 
--    rdreq   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrclk   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    wrreq   : IN STD_LOGIC ;
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdempty : OUT STD_LOGIC ;
 
--    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    rdusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrfull  : OUT STD_LOGIC ;
 
--    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--    wrusedw : OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
 
--  );
 
--  );
 
--  END COMPONENT;
 
--  END COMPONENT;
 
 
 
 
 
 
 
 
 
END tech_fifo_component_pkg;
 
END tech_fifo_component_pkg;

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