| Line 16... |
Line 16... |
-- See the License for the specific language governing permissions and
|
-- See the License for the specific language governing permissions and
|
-- limitations under the License.
|
-- limitations under the License.
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib;
|
LIBRARY IEEE, common_pkg_lib, common_components_lib;
|
USE IEEE.std_logic_1164.ALL;
|
USE IEEE.std_logic_1164.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE technology_lib.technology_pkg.ALL;
|
--USE technology_lib.technology_pkg.ALL;
|
USE technology_lib.technology_select_pkg.ALL;
|
--USE technology_lib.technology_select_pkg.ALL;
|
USE work.tech_mult_component_pkg.ALL;
|
USE work.tech_mult_component_pkg.ALL;
|
|
|
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
|
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
|
LIBRARY ip_stratixiv_mult_lib;
|
--LIBRARY ip_stratixiv_mult_lib;
|
--LIBRARY ip_arria10_mult_lib;
|
--LIBRARY ip_arria10_mult_lib;
|
--LIBRARY ip_arria10_mult_rtl_lib;
|
--LIBRARY ip_arria10_mult_rtl_lib;
|
--LIBRARY ip_arria10_complex_mult_altmult_complex_150;
|
--LIBRARY ip_arria10_complex_mult_altmult_complex_150;
|
--LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
|
--LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
|
--LIBRARY ip_arria10_complex_mult_rtl_lib;
|
--LIBRARY ip_arria10_complex_mult_rtl_lib;
|
| Line 36... |
Line 36... |
|
|
ENTITY tech_complex_mult IS
|
ENTITY tech_complex_mult IS
|
GENERIC (
|
GENERIC (
|
g_sim : BOOLEAN := TRUE;
|
g_sim : BOOLEAN := TRUE;
|
g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
|
g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
|
g_technology : NATURAL := c_tech_select_default;
|
g_technology : NATURAL := 0;
|
g_variant : STRING := "IP";
|
g_variant : STRING := "IP";
|
g_in_a_w : POSITIVE;
|
g_in_a_w : POSITIVE;
|
g_in_b_w : POSITIVE;
|
g_in_b_w : POSITIVE;
|
g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
|
g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
|
g_conjugate_b : BOOLEAN := FALSE;
|
g_conjugate_b : BOOLEAN := FALSE;
|
| Line 84... |
Line 84... |
SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
|
SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
|
SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
|
SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
|
|
|
begin
|
begin
|
|
|
gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
|
gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=0 AND g_variant="IP") GENERATE
|
|
|
-- Adapt DSP input widths
|
-- Adapt DSP input widths
|
ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
|
ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
|
ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
|
ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
|
br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
|
br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
|
| Line 111... |
Line 111... |
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
|
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
|
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
|
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
|
|
|
END GENERATE;
|
END GENERATE;
|
|
|
gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
|
gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=0 AND g_variant="RTL") GENERATE
|
u0 : ip_stratixiv_complex_mult_rtl
|
u0 : ip_stratixiv_complex_mult_rtl
|
GENERIC MAP(
|
GENERIC MAP(
|
g_in_a_w => g_in_a_w,
|
g_in_a_w => g_in_a_w,
|
g_in_b_w => g_in_b_w,
|
g_in_b_w => g_in_b_w,
|
g_out_p_w => g_out_p_w,
|
g_out_p_w => g_out_p_w,
|
