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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib;
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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--USE technology_lib.technology_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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USE work.tech_mult_component_pkg.ALL;
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USE work.tech_mult_component_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_mult_lib;
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--LIBRARY ip_stratixiv_mult_lib;
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--LIBRARY ip_arria10_mult_lib;
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--LIBRARY ip_arria10_mult_lib;
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--LIBRARY ip_arria10_mult_rtl_lib;
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--LIBRARY ip_arria10_mult_rtl_lib;
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--LIBRARY ip_arria10_complex_mult_altmult_complex_150;
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--LIBRARY ip_arria10_complex_mult_altmult_complex_150;
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--LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
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--LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
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--LIBRARY ip_arria10_complex_mult_rtl_lib;
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--LIBRARY ip_arria10_complex_mult_rtl_lib;
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Line 36... |
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ENTITY tech_complex_mult IS
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ENTITY tech_complex_mult IS
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GENERIC (
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GENERIC (
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g_sim : BOOLEAN := TRUE;
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g_sim : BOOLEAN := TRUE;
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g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
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g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_variant : STRING := "IP";
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g_variant : STRING := "IP";
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g_in_a_w : POSITIVE;
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g_in_a_w : POSITIVE;
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g_in_b_w : POSITIVE;
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g_in_b_w : POSITIVE;
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g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
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g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
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g_conjugate_b : BOOLEAN := FALSE;
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g_conjugate_b : BOOLEAN := FALSE;
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Line 84... |
SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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begin
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begin
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gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
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gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=0 AND g_variant="IP") GENERATE
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-- Adapt DSP input widths
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-- Adapt DSP input widths
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ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
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ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
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ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
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ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
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br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
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br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
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Line 111... |
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
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result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
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result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
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result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
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END GENERATE;
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END GENERATE;
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gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
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gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=0 AND g_variant="RTL") GENERATE
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u0 : ip_stratixiv_complex_mult_rtl
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u0 : ip_stratixiv_complex_mult_rtl
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GENERIC MAP(
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GENERIC MAP(
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g_in_a_w => g_in_a_w,
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g_in_a_w => g_in_a_w,
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g_in_b_w => g_in_b_w,
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g_in_b_w => g_in_b_w,
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g_out_p_w => g_out_p_w,
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g_out_p_w => g_out_p_w,
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