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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_ram_lib;
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE work.common_ram_pkg.ALL;
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USE work.common_ram_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_ram_crw_crw IS
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ENTITY common_ram_crw_crw IS
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0;
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g_ram : t_c_mem := c_mem_ram;
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g_ram : t_c_mem := c_mem_ram;
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g_init_file : STRING := "UNUSED";
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g_init_file : STRING := "UNUSED";
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g_true_dual_port : BOOLEAN := TRUE
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g_true_dual_port : BOOLEAN := TRUE
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);
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);
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PORT (
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PORT (
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REPORT "common_ram_crw_crw : only support read latency >= 1"
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REPORT "common_ram_crw_crw : only support read latency >= 1"
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SEVERITY FAILURE;
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SEVERITY FAILURE;
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-- memory access
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-- memory access
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gen_true_dual_port : IF g_true_dual_port = TRUE GENERATE
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gen_true_dual_port : IF g_true_dual_port = TRUE GENERATE
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u_ram : ENTITY tech_ram_lib.tech_memory_ram_crw_crw
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u_ram : ENTITY work.tech_memory_ram_crw_crw
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_adr_w => g_ram.adr_w,
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g_adr_w => g_ram.adr_w,
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g_dat_w => g_ram.dat_w,
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g_dat_w => g_ram.dat_w,
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g_nof_words => g_ram.nof_dat,
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g_nof_words => g_ram.nof_dat,
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| Line 101... |
Line 101... |
q_b => ram_rd_dat_b
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q_b => ram_rd_dat_b
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);
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);
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END GENERATE;
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END GENERATE;
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gen_simple_dual_port : IF g_true_dual_port = FALSE GENERATE
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gen_simple_dual_port : IF g_true_dual_port = FALSE GENERATE
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u_ram : ENTITY tech_ram_lib.tech_memory_ram_cr_cw
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u_ram : ENTITY work.tech_memory_ram_cr_cw
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GENERIC MAP (
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GENERIC MAP (
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g_technology => g_technology,
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g_technology => g_technology,
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g_adr_w => g_ram.adr_w,
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g_adr_w => g_ram.adr_w,
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g_dat_w => g_ram.dat_w,
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g_dat_w => g_ram.dat_w,
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g_nof_words => g_ram.nof_dat,
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g_nof_words => g_ram.nof_dat,
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