| Line 16... |
Line 16... |
-- See the License for the specific language governing permissions and
|
-- See the License for the specific language governing permissions and
|
-- limitations under the License.
|
-- limitations under the License.
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
LIBRARY IEEE, common_pkg_lib, common_components_lib, common_ram_lib, technology_lib, tech_ram_lib;
|
LIBRARY IEEE, common_pkg_lib, common_components_lib;
|
USE IEEE.std_logic_1164.ALL;
|
USE IEEE.std_logic_1164.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE common_pkg_lib.common_pkg.ALL;
|
USE common_ram_lib.common_ram_pkg.ALL;
|
USE work.common_ram_pkg.ALL;
|
USE technology_lib.technology_select_pkg.ALL;
|
--USE technology_lib.technology_select_pkg.ALL;
|
|
|
ENTITY common_ram_crw_crw_ratio IS
|
ENTITY common_ram_crw_crw_ratio IS
|
GENERIC (
|
GENERIC (
|
g_technology : NATURAL := c_tech_select_default;
|
g_technology : NATURAL := 0;
|
g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
|
g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
|
g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
|
g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
|
g_init_file : STRING := "UNUSED"
|
g_init_file : STRING := "UNUSED"
|
);
|
);
|
PORT (
|
PORT (
|
| Line 80... |
Line 80... |
ASSERT g_ram_a.latency = g_ram_b.latency
|
ASSERT g_ram_a.latency = g_ram_b.latency
|
REPORT "common_ram_crw_crw_ratio : only support same read latency for both ports"
|
REPORT "common_ram_crw_crw_ratio : only support same read latency for both ports"
|
SEVERITY FAILURE;
|
SEVERITY FAILURE;
|
|
|
-- memory access
|
-- memory access
|
u_ramk : ENTITY tech_ram_lib.tech_memory_ram_crwk_crw
|
u_ramk : ENTITY work.tech_memory_ram_crwk_crw
|
GENERIC MAP (
|
GENERIC MAP (
|
g_technology => g_technology,
|
g_technology => g_technology,
|
g_adr_a_w => g_ram_a.adr_w,
|
g_adr_a_w => g_ram_a.adr_w,
|
g_adr_b_w => g_ram_b.adr_w,
|
g_adr_b_w => g_ram_b.adr_w,
|
g_dat_a_w => g_ram_a.dat_w,
|
g_dat_a_w => g_ram_a.dat_w,
|
