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--programming logic devices manufactured by Altera and sold by
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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--applicable agreement for further details.
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LIBRARY ieee;
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LIBRARY ieee, common_pkg_lib;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE common_pkg_lib.common_pkg.ALL;
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LIBRARY altera_mf;
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LIBRARY altera_mf;
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USE altera_mf.all;
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USE altera_mf.all;
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LIBRARY technology_lib;
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--LIBRARY technology_lib;
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USE technology_lib.technology_pkg.ALL;
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--USE technology_lib.technology_pkg.ALL;
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ENTITY ip_stratixiv_ram_crw_crw IS
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ENTITY ip_stratixiv_ram_crw_crw IS
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GENERIC (
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GENERIC (
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g_adr_w : NATURAL := 5;
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g_adr_w : NATURAL := 5;
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g_dat_w : NATURAL := 8;
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g_dat_w : NATURAL := 8;
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END ip_stratixiv_ram_crw_crw;
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END ip_stratixiv_ram_crw_crw;
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ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
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ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
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CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
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CONSTANT c_outdata_reg_a : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
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CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
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CONSTANT c_outdata_reg_b : STRING := sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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