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[/] [astron_ram/] [trunk/] [tech_memory_ram_crw_crw.vhd] - Diff between revs 3 and 4

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-- See the License for the specific language governing permissions and
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- limitations under the License.
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
LIBRARY ieee, technology_lib;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164.all;
USE work.tech_memory_component_pkg.ALL;
USE work.tech_memory_component_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
--USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--USE technology_lib.technology_select_pkg.ALL;
 
 
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_stratixiv_ram_lib;
--LIBRARY ip_arria10_ram_lib;
--LIBRARY ip_arria10_ram_lib;
--LIBRARY ip_arria10_e3sge3_ram_lib;
--LIBRARY ip_arria10_e3sge3_ram_lib;
--LIBRARY ip_arria10_e1sg_ram_lib;
--LIBRARY ip_arria10_e1sg_ram_lib;
 
 
ENTITY tech_memory_ram_crw_crw IS
ENTITY tech_memory_ram_crw_crw IS
  GENERIC (
  GENERIC (
    g_technology : NATURAL := c_tech_select_default;
    g_technology : NATURAL := 0; --c_tech_select_default;
    g_adr_w      : NATURAL := 5;
    g_adr_w      : NATURAL := 5;
    g_dat_w      : NATURAL := 8;
    g_dat_w      : NATURAL := 8;
    g_nof_words  : NATURAL := 2**5;
    g_nof_words  : NATURAL := 2**5;
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
    g_init_file  : STRING  := "UNUSED"
    g_init_file  : STRING  := "UNUSED"
Line 61... Line 61...
 
 
ARCHITECTURE str OF tech_memory_ram_crw_crw IS
ARCHITECTURE str OF tech_memory_ram_crw_crw IS
 
 
BEGIN
BEGIN
 
 
  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
  gen_ip_stratixiv : IF g_technology=0 GENERATE
    u0 : ip_stratixiv_ram_crw_crw
    u0 : ip_stratixiv_ram_crw_crw
    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
  END GENERATE;
  END GENERATE;
 
 

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