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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY ieee, technology_lib;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE work.tech_memory_component_pkg.ALL;
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USE work.tech_memory_component_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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--USE technology_lib.technology_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_ram_lib;
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--LIBRARY ip_stratixiv_ram_lib;
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--LIBRARY ip_arria10_ram_lib;
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--LIBRARY ip_arria10_ram_lib;
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--LIBRARY ip_arria10_e3sge3_ram_lib;
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--LIBRARY ip_arria10_e3sge3_ram_lib;
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--LIBRARY ip_arria10_e1sg_ram_lib;
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--LIBRARY ip_arria10_e1sg_ram_lib;
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ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
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ENTITY tech_memory_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
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GENERIC (
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_technology : NATURAL := 0; --c_tech_select_default;
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g_adr_a_w : NATURAL := 5;
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g_adr_a_w : NATURAL := 5;
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g_dat_a_w : NATURAL := 32;
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g_dat_a_w : NATURAL := 32;
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g_adr_b_w : NATURAL := 7;
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g_adr_b_w : NATURAL := 7;
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g_dat_b_w : NATURAL := 8;
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g_dat_b_w : NATURAL := 8;
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g_nof_words_a : NATURAL := 2**5;
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g_nof_words_a : NATURAL := 2**5;
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Line 63... |
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ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
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ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
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BEGIN
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BEGIN
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gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
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gen_ip_stratixiv : IF g_technology=0 GENERATE
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u0 : ip_stratixiv_ram_crwk_crw
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u0 : ip_stratixiv_ram_crwk_crw
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GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
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PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
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END GENERATE;
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END GENERATE;
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