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[/] [astron_requantizer/] [trunk/] [dp_requantize.vhd] - Diff between revs 3 and 4

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-- See the License for the specific language governing permissions and
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- limitations under the License.
--
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
 
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, common_requantize_lib, dp_pipeline_lib;
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, astron_pipeline_lib;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_1164.all;
USE dp_pkg_lib.dp_stream_pkg.ALL;
USE dp_pkg_lib.dp_stream_pkg.ALL;
--USE common_lib.all;     
--USE common_lib.all;     
USE common_pkg_lib.common_pkg.ALL;
USE common_pkg_lib.common_pkg.ALL;
 
 
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  ---------------------------------------------------------------
  ---------------------------------------------------------------
  -- Requantize the sosi data field
  -- Requantize the sosi data field
  ---------------------------------------------------------------
  ---------------------------------------------------------------
  gen_requantize_data : IF g_complex=FALSE GENERATE
  gen_requantize_data : IF g_complex=FALSE GENERATE
    u_requantize_data : ENTITY common_requantize_lib.common_requantize
    u_requantize_data : ENTITY work.common_requantize
    GENERIC MAP (
    GENERIC MAP (
      g_representation      => g_representation,
      g_representation      => g_representation,
      g_lsb_w               => g_lsb_w,
      g_lsb_w               => g_lsb_w,
      g_lsb_round           => g_lsb_round,
      g_lsb_round           => g_lsb_round,
      g_lsb_round_clip      => g_lsb_round_clip,
      g_lsb_round_clip      => g_lsb_round_clip,
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  ---------------------------------------------------------------
  ---------------------------------------------------------------
  -- Requantize the sosi complex fields
  -- Requantize the sosi complex fields
  ---------------------------------------------------------------
  ---------------------------------------------------------------
  gen_requantize_complex : IF g_complex=TRUE GENERATE
  gen_requantize_complex : IF g_complex=TRUE GENERATE
    u_requantize_re: ENTITY common_requantize_lib.common_requantize
    u_requantize_re: ENTITY work.common_requantize
    GENERIC MAP (
    GENERIC MAP (
      g_representation      => g_representation,
      g_representation      => g_representation,
      g_lsb_w               => g_lsb_w,
      g_lsb_w               => g_lsb_w,
      g_lsb_round           => g_lsb_round,
      g_lsb_round           => g_lsb_round,
      g_lsb_round_clip      => g_lsb_round_clip,
      g_lsb_round_clip      => g_lsb_round_clip,
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      in_dat     => snk_in.re,
      in_dat     => snk_in.re,
      out_dat    => quantized_re,
      out_dat    => quantized_re,
      out_ovr    => out_ovr_re
      out_ovr    => out_ovr_re
    );
    );
 
 
    u_requantize_im: ENTITY common_requantize_lib.common_requantize
    u_requantize_im: ENTITY work.common_requantize
    GENERIC MAP (
    GENERIC MAP (
      g_representation      => g_representation,
      g_representation      => g_representation,
      g_lsb_w               => g_lsb_w,
      g_lsb_w               => g_lsb_w,
      g_lsb_round           => g_lsb_round,
      g_lsb_round           => g_lsb_round,
      g_lsb_round_clip      => g_lsb_round_clip,
      g_lsb_round_clip      => g_lsb_round_clip,
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  --------------------------------------------------------------
  --------------------------------------------------------------
  -- Pipeline to align the other sosi fields
  -- Pipeline to align the other sosi fields
  --------------------------------------------------------------
  --------------------------------------------------------------
  u_dp_pipeline : ENTITY dp_pipeline_lib.dp_pipeline
  u_dp_pipeline : ENTITY astron_pipeline_lib.dp_pipeline
  GENERIC MAP (
  GENERIC MAP (
    g_pipeline   => c_pipeline  -- 0 for wires, > 0 for registers, 
    g_pipeline   => c_pipeline  -- 0 for wires, > 0 for registers, 
  )
  )
  PORT MAP (
  PORT MAP (
    rst          => rst,
    rst          => rst,

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