Line 33... |
Line 33... |
-- stages in the FFT. In other words: the fft_wide_unit_control unit
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-- stages in the FFT. In other words: the fft_wide_unit_control unit
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-- is not capable of handling more than one sync pulse at a time.
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-- is not capable of handling more than one sync pulse at a time.
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--
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--
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--
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--
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library IEEE, common_pkg_lib, common_ram_lib, common_fifo_lib, dp_pkg_lib;
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library IEEE, common_pkg_lib, astron_ram_lib, astron_fifo_lib, dp_pkg_lib;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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use IEEE.numeric_std.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use common_ram_lib.common_ram_pkg.ALL;
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use astron_ram_lib.common_ram_pkg.ALL;
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use dp_pkg_lib.dp_stream_pkg.ALL;
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use dp_pkg_lib.dp_stream_pkg.ALL;
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use work.fft_pkg.ALL;
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use work.fft_pkg.ALL;
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entity fft_wide_unit_control is
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entity fft_wide_unit_control is
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generic (
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generic (
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Line 93... |
Line 93... |
begin
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begin
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- INPUT FIFO FOR BSN
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-- INPUT FIFO FOR BSN
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---------------------------------------------------------------
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---------------------------------------------------------------
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u_bsn_fifo : entity common_fifo_lib.common_fifo_sc
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u_bsn_fifo : entity astron_fifo_lib.common_fifo_sc
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generic map (
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generic map (
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_reset => FALSE,
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g_reset => FALSE,
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g_init => FALSE,
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g_init => FALSE,
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g_dat_w => c_dp_stream_bsn_w,
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g_dat_w => c_dp_stream_bsn_w,
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Line 117... |
Line 117... |
);
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);
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- INPUT FIFO FOR ERR
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-- INPUT FIFO FOR ERR
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---------------------------------------------------------------
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---------------------------------------------------------------
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u_error_fifo : entity common_fifo_lib.common_fifo_sc
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u_error_fifo : entity astron_fifo_lib.common_fifo_sc
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generic map (
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generic map (
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_reset => FALSE,
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g_reset => FALSE,
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g_init => FALSE,
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g_init => FALSE,
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g_dat_w => c_dp_stream_error_w,
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g_dat_w => c_dp_stream_error_w,
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Line 141... |
Line 141... |
);
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);
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- FIFO FOR SYNC-BSN
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-- FIFO FOR SYNC-BSN
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---------------------------------------------------------------
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---------------------------------------------------------------
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u_sync_bsn_fifo : entity common_fifo_lib.common_fifo_sc
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u_sync_bsn_fifo : entity astron_fifo_lib.common_fifo_sc
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generic map (
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generic map (
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_use_lut => TRUE, -- Make this FIFO in logic, since it's only 4 words deep.
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g_reset => FALSE,
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g_reset => FALSE,
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g_init => FALSE,
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g_init => FALSE,
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g_dat_w => c_dp_stream_bsn_w,
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g_dat_w => c_dp_stream_bsn_w,
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Line 165... |
Line 165... |
);
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);
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---------------------------------------------------------------
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---------------------------------------------------------------
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-- CREATE READ-AHEAD FIFO INTERFACE FOR SYNC-BSN
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-- CREATE READ-AHEAD FIFO INTERFACE FOR SYNC-BSN
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---------------------------------------------------------------
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---------------------------------------------------------------
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u_fifo_adapter : entity common_fifo_lib.common_fifo_rd
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u_fifo_adapter : entity astron_fifo_lib.common_fifo_rd
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generic map (
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generic map (
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g_dat_w => c_dp_stream_bsn_w
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g_dat_w => c_dp_stream_bsn_w
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)
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)
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port map(
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port map(
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rst => rst,
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rst => rst,
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