| Line 79... |
Line 79... |
wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][SCN-1:0] sim4, wim4, nim4, eim4, lim4;
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wire [MN-1:0][SCN-1:0] sim4, wim4, nim4, eim4, lim4;
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wire [MN-1:0][SCN-1:0] sima, wima, nima, eima, lima;
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wire [MN-1:0][SCN-1:0] sima, wima, nima, eima, lima;
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wire [MN-1:0][SCN-1:0] sima4, wima4, nima4, eima4, lima4;
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wire [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4;
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wire [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4;
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wire [MN-1:0][4:0][SCN-1:0] cmo4;
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wire [MN-1:0][4:0][SCN-1:0] cmo4, cmi4, cmia, cmoa, cmoa4;
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`else
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`else
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wire [MN-1:0] sim4, wim4, nim4, eim4, lim4;
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wire [MN-1:0] sim4, wim4, nim4, eim4, lim4;
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wire [MN-1:0] sima, wima, nima, eima, lima;
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wire [MN-1:0] sima, wima, nima, eima, lima;
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wire [MN-1:0] sima4, wima4, nima4, eima4, lima4;
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wire [NN-1:0] soa4, woa4, noa4, eoa4, loa4;
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wire [NN-1:0] soa4, woa4, noa4, eoa4, loa4;
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wire [MN-1:0][4:0] cmo4;
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wire [MN-1:0][4:0] cmo4, cmi4, cmia, cmoa, cmoa4;
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][3:0] simdec, nimdec, limdec; // the routing requests
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wire [MN-1:0][3:0] simdec, nimdec, limdec; // the routing requests
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wire [MN-1:0][1:0] wimdec, eimdec; // the routing requests
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wire [MN-1:0][1:0] wimdec, eimdec; // the routing requests
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| Line 281... |
Line 283... |
assign so0[i] = cmo0[i][0];
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assign so0[i] = cmo0[i][0];
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assign so1[i] = cmo1[i][0];
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assign so1[i] = cmo1[i][0];
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assign so2[i] = cmo2[i][0];
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assign so2[i] = cmo2[i][0];
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assign so3[i] = cmo3[i][0];
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assign so3[i] = cmo3[i][0];
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assign cmoa[i][0] = soa[i];
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assign cmoa[i][0] = soa[i];
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assign cmoa[i][0] = soa4[i];
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assign cmoa4[i][0] = soa4[i];
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assign wo0[i] = cmo0[i][1];
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assign wo0[i] = cmo0[i][1];
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assign wo1[i] = cmo1[i][1];
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assign wo1[i] = cmo1[i][1];
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assign wo2[i] = cmo2[i][1];
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assign wo2[i] = cmo2[i][1];
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assign wo3[i] = cmo3[i][1];
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assign wo3[i] = cmo3[i][1];
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assign cmoa[i][1] = woa[i];
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assign cmoa[i][1] = woa[i];
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assign cmoa[i][1] = woa4[i];
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assign cmoa4[i][1] = woa4[i];
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assign no0[i] = cmo0[i][2];
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assign no0[i] = cmo0[i][2];
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assign no1[i] = cmo1[i][2];
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assign no1[i] = cmo1[i][2];
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assign no2[i] = cmo2[i][2];
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assign no2[i] = cmo2[i][2];
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assign no3[i] = cmo3[i][2];
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assign no3[i] = cmo3[i][2];
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assign cmoa[i][2] = noa[i];
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assign cmoa[i][2] = noa[i];
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assign cmoa[i][2] = noa4[i];
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assign cmoa4[i][2] = noa4[i];
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assign eo0[i] = cmo0[i][3];
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assign eo0[i] = cmo0[i][3];
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assign eo1[i] = cmo1[i][3];
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assign eo1[i] = cmo1[i][3];
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assign eo2[i] = cmo2[i][3];
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assign eo2[i] = cmo2[i][3];
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assign eo3[i] = cmo3[i][3];
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assign eo3[i] = cmo3[i][3];
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assign cmoa[i][3] = eoa[i];
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assign cmoa[i][3] = eoa[i];
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assign cmoa[i][3] = eoa4[i];
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assign cmoa4[i][3] = eoa4[i];
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assign lo0[i] = cmo0[i][4];
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assign lo0[i] = cmo0[i][4];
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assign lo1[i] = cmo1[i][4];
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assign lo1[i] = cmo1[i][4];
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assign lo2[i] = cmo2[i][4];
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assign lo2[i] = cmo2[i][4];
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assign lo3[i] = cmo3[i][4];
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assign lo3[i] = cmo3[i][4];
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assign cmoa[i][4] = loa[i];
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assign cmoa[i][4] = loa[i];
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assign cmoa[i][4] = loa4[i];
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assign cmoa4[i][4] = loa4[i];
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assign sims[i] = {cms[i][4],cms[i][3],cms[i][2],cms[i][1]};
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assign sims[i] = {cms[i][4],cms[i][3],cms[i][2],cms[i][1]};
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assign wims[i] = {cms[i][4],cms[i][3]};
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assign wims[i] = {cms[i][4],cms[i][3]};
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assign nims[i] = {cms[i][4],cms[i][3],cms[i][1],cms[i][0]};
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assign nims[i] = {cms[i][4],cms[i][3],cms[i][1],cms[i][0]};
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assign eims[i] = {cms[i][4],cms[i][1]};
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assign eims[i] = {cms[i][4],cms[i][1]};
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