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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module clos (/*AUTOARG*/);
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module clos (/*AUTOARG*/
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, soa4, woa4, noa4, eoa4, loa4, sdec, ndec, ldec,
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wdec, edec
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);
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parameter MN = 2; // number of CMs
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parameter MN = 2; // number of CMs
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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// `ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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// `endif
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`else
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`else
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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// `ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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// `endif
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
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input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
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input [NN-1:0][1:0] wdec, edec; // the routing requests
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input [NN-1:0][1:0] wdec, edec; // the routing requests
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