OpenCores

Rev 69	Rev 70
Line 18...	Line 18...
`*/`	`*/`

`// the router structure definitions`	`// the router structure definitions`
`include "define.v"	`include "define.v"

`module cm (/AUTOARG/`	`module cm (`
`// Outputs`	`// Outputs`
`do0, do1, do2, do3, dia, do4,`	`do0, do1, do2, do3, dia, do4,`
`// Inputs`	`// Inputs`
`di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,`	`di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,`
	`ifndef ENABLE_CRRD
	`cms,`
	`endif
`rst_n`	`rst_n`
`);`	`);`

`parameter KN = 5; // dummy parameter, the number of IMs`	`parameter KN = 5; // dummy parameter, the number of IMs`
`parameter DW = 8; // the data width of each IP`	`parameter DW = 8; // the data width of each IP`
Line 53...	Line 56...
`output [KN-1:0] cms; // the state feedback to IMs`	`output [KN-1:0] cms; // the state feedback to IMs`
`endif	`endif

`input rst_n; // global active low reset`	`input rst_n; // global active low reset`

`wire [KN-1:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; // the data output of CM`
`ifdef ENABLE_CHANNEL_SLICING
`wire [KN-1:0][SCN-1:0] cmo4, cmoa, cmoa4; // data and ack wires`
`else
`wire [KN-1:0] cmo4, cmoa, cmoa4; // data and ack wires`
`endif
`wire [3:0] wcfg, ecfg, lcfg; // switch configuration`	`wire [3:0] wcfg, ecfg, lcfg; // switch configuration`
`wire [1:0] scfg, ncfg; // switch configuration`	`wire [1:0] scfg, ncfg; // switch configuration`

`genvar i, j;`	`genvar i, j;`

`// data switch`	`// data switch`
`dcb_xy #(.VCN(1), .VCW(DW))`	`dcb_xy #(.VCN(1), .VCW(DW))`
`CM (`	`CMDCB (`
`.sia ( dia[i][0] ),`	`.sia ( dia[i][0] ),`
`.wia ( dia[i][1] ),`	`.wia ( dia[i][1] ),`
`.nia ( dia[i][2] ),`	`.nia ( dia[i][2] ),`
`.eia ( dia[i][3] ),`	`.eia ( dia[i][3] ),`
`.lia ( dia[i][4] ),`	`.lia ( dia[i][4] ),`
`.so0 ( cmo0[i][0] ),`	`.so0 ( do0[i][0] ),`
`.so1 ( cmo1[i][0] ),`	`.so1 ( do1[i][0] ),`
`.so2 ( cmo2[i][0] ),`	`.so2 ( do2[i][0] ),`
`.so3 ( cmo3[i][0] ),`	`.so3 ( do3[i][0] ),`
`.so4 ( cmo4[i][0] ),`	`.so4 ( do4[i][0] ),`
`.wo0 ( cmo0[i][1] ),`	`.wo0 ( do0[i][1] ),`
`.wo1 ( cmo1[i][1] ),`	`.wo1 ( do1[i][1] ),`
`.wo2 ( cmo2[i][1] ),`	`.wo2 ( do2[i][1] ),`
`.wo3 ( cmo3[i][1] ),`	`.wo3 ( do3[i][1] ),`
`.wo4 ( cmo4[i][1] ),`	`.wo4 ( do4[i][1] ),`
`.no0 ( cmo0[i][2] ),`	`.no0 ( do0[i][2] ),`
`.no1 ( cmo1[i][2] ),`	`.no1 ( do1[i][2] ),`
`.no2 ( cmo2[i][2] ),`	`.no2 ( do2[i][2] ),`
`.no3 ( cmo3[i][2] ),`	`.no3 ( do3[i][2] ),`
`.no4 ( cmo4[i][2] ),`	`.no4 ( do4[i][2] ),`
`.eo0 ( cmo0[i][3] ),`	`.eo0 ( do0[i][3] ),`
`.eo1 ( cmo1[i][3] ),`	`.eo1 ( do1[i][3] ),`
`.eo2 ( cmo2[i][3] ),`	`.eo2 ( do2[i][3] ),`
`.eo3 ( cmo3[i][3] ),`	`.eo3 ( do3[i][3] ),`
`.eo4 ( cmo4[i][3] ),`	`.eo4 ( do4[i][3] ),`
`.lo0 ( cmo0[i][4] ),`	`.lo0 ( do0[i][4] ),`
`.lo1 ( cmo1[i][4] ),`	`.lo1 ( do1[i][4] ),`
`.lo2 ( cmo2[i][4] ),`	`.lo2 ( do2[i][4] ),`
`.lo3 ( cmo3[i][4] ),`	`.lo3 ( do3[i][4] ),`
`.lo4 ( cmo4[i][4] ),`	`.lo4 ( do4[i][4] ),`
`.si0 ( di0[i][0] ),`	`.si0 ( di0[i][0] ),`
`.si1 ( di1[i][0] ),`	`.si1 ( di1[i][0] ),`
`.si2 ( di2[i][0] ),`	`.si2 ( di2[i][0] ),`
`.si3 ( di3[i][0] ),`	`.si3 ( di3[i][0] ),`
`.si4 ( di4[i][0] ),`	`.si4 ( di4[i][0] ),`
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`.li0 ( di0[i][4] ),`	`.li0 ( di0[i][4] ),`
`.li1 ( di1[i][4] ),`	`.li1 ( di1[i][4] ),`
`.li2 ( di2[i][4] ),`	`.li2 ( di2[i][4] ),`
`.li3 ( di3[i][4] ),`	`.li3 ( di3[i][4] ),`
`.li4 ( di4[i][4] ),`	`.li4 ( di4[i][4] ),`
`.soa ( cmoa[i][0] ),`	`.soa ( doa[i][0] ),`
`.woa ( cmoa[i][1] ),`	`.woa ( doa[i][1] ),`
`.noa ( cmoa[i][2] ),`	`.noa ( doa[i][2] ),`
`.eoa ( cmoa[i][3] ),`	`.eoa ( doa[i][3] ),`
`.loa ( cmoa[i][4] ),`	`.loa ( doa[i][4] ),`
`.soa4 ( cmoa4[i][0] ),`	`.soa4 ( doa4[i][0] ),`
`.woa4 ( cmoa4[i][1] ),`	`.woa4 ( doa4[i][1] ),`
`.noa4 ( cmoa4[i][2] ),`	`.noa4 ( doa4[i][2] ),`
`.eoa4 ( cmoa4[i][3] ),`	`.eoa4 ( doa4[i][3] ),`
`.loa4 ( cmoa4[i][4] ),`	`.loa4 ( doa4[i][4] ),`
`.wcfg ( wcfg[i] ),`	`.wcfg ( wcfg[i] ),`
`.ecfg ( ecfg[i] ),`	`.ecfg ( ecfg[i] ),`
`.lcfg ( lcfg[i] ),`	`.lcfg ( lcfg[i] ),`
`.scfg ( scfg[i] ),`	`.scfg ( scfg[i] ),`
`.ncfg ( ncfg[i] )`	`.ncfg ( ncfg[i] )`
Line 161...	Line 158...
`.nr ( ndec ),`	`.nr ( ndec ),`
`.er ( edec ),`	`.er ( edec ),`
`.lr ( ldec )`	`.lr ( ldec )`
`);`	`);`



`endmodule // cm`	`endmodule // cm`

`No newline at end of file`	`No newline at end of file`

Line 18...

*/

*/

// the router structure definitions

// the router structure definitions

`include "define.v"

`include "define.v"

module cm (/*AUTOARG*/

module cm (

   // Outputs

   // Outputs

   do0, do1, do2, do3, dia, do4,

   do0, do1, do2, do3, dia, do4,

   // Inputs

   // Inputs

   di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,

   di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,

`ifndef ENABLE_CRRD

   cms,

`endif

   rst_n

   rst_n

);

);

   parameter KN = 5;           // dummy parameter, the number of IMs

   parameter KN = 5;           // dummy parameter, the number of IMs

   parameter DW = 8;           // the data width of each IP

   parameter DW = 8;           // the data width of each IP

Line 53...

Line 56...

   output [KN-1:0]             cms; // the state feedback to IMs

   output [KN-1:0]             cms; // the state feedback to IMs

`endif

`endif

   input                      rst_n; // global active low reset

   input                      rst_n; // global active low reset

   wire [KN-1:0][SCN-1:0]     cmo0, cmo1, cmo2, cmo3; // the data output of CM

`ifdef ENABLE_CHANNEL_SLICING

   wire [KN-1:0][SCN-1:0]     cmo4, cmoa, cmoa4; // data and ack wires

`else

   wire [KN-1:0]               cmo4, cmoa, cmoa4; // data and ack wires

`endif

   wire [3:0]                  wcfg, ecfg, lcfg; // switch configuration

   wire [3:0]                  wcfg, ecfg, lcfg; // switch configuration

   wire [1:0]                  scfg, ncfg;       // switch configuration

   wire [1:0]                  scfg, ncfg;       // switch configuration

   genvar                     i, j;

   genvar                     i, j;

   // data switch

   // data switch

   dcb_xy #(.VCN(1), .VCW(DW))

   dcb_xy #(.VCN(1), .VCW(DW))

   CM (

   CMDCB (

       .sia   ( dia[i][0]    ),

       .sia   ( dia[i][0]    ),

       .wia   ( dia[i][1]    ),

       .wia   ( dia[i][1]    ),

       .nia   ( dia[i][2]    ),

       .nia   ( dia[i][2]    ),

       .eia   ( dia[i][3]    ),

       .eia   ( dia[i][3]    ),

       .lia   ( dia[i][4]    ),

       .lia   ( dia[i][4]    ),

       .so0   ( cmo0[i][0]   ),

          .so0   ( do0[i][0]    ),

       .so1   ( cmo1[i][0]   ),

          .so1   ( do1[i][0]    ),

       .so2   ( cmo2[i][0]   ),

          .so2   ( do2[i][0]    ),

       .so3   ( cmo3[i][0]   ),

          .so3   ( do3[i][0]    ),

       .so4   ( cmo4[i][0]   ),

          .so4   ( do4[i][0]    ),

       .wo0   ( cmo0[i][1]   ),

          .wo0   ( do0[i][1]    ),

       .wo1   ( cmo1[i][1]   ),

          .wo1   ( do1[i][1]    ),

       .wo2   ( cmo2[i][1]   ),

          .wo2   ( do2[i][1]    ),

       .wo3   ( cmo3[i][1]   ),

          .wo3   ( do3[i][1]    ),

       .wo4   ( cmo4[i][1]   ),

          .wo4   ( do4[i][1]    ),

       .no0   ( cmo0[i][2]   ),

          .no0   ( do0[i][2]    ),

       .no1   ( cmo1[i][2]   ),

          .no1   ( do1[i][2]    ),

       .no2   ( cmo2[i][2]   ),

          .no2   ( do2[i][2]    ),

       .no3   ( cmo3[i][2]   ),

          .no3   ( do3[i][2]    ),

       .no4   ( cmo4[i][2]   ),

          .no4   ( do4[i][2]    ),

       .eo0   ( cmo0[i][3]   ),

          .eo0   ( do0[i][3]    ),

       .eo1   ( cmo1[i][3]   ),

          .eo1   ( do1[i][3]    ),

       .eo2   ( cmo2[i][3]   ),

          .eo2   ( do2[i][3]    ),

       .eo3   ( cmo3[i][3]   ),

          .eo3   ( do3[i][3]    ),

       .eo4   ( cmo4[i][3]   ),

          .eo4   ( do4[i][3]    ),

       .lo0   ( cmo0[i][4]   ),

          .lo0   ( do0[i][4]    ),

       .lo1   ( cmo1[i][4]   ),

          .lo1   ( do1[i][4]    ),

       .lo2   ( cmo2[i][4]   ),

          .lo2   ( do2[i][4]    ),

       .lo3   ( cmo3[i][4]   ),

          .lo3   ( do3[i][4]    ),

       .lo4   ( cmo4[i][4]   ),

          .lo4   ( do4[i][4]    ),

       .si0   ( di0[i][0]    ),

       .si0   ( di0[i][0]    ),

       .si1   ( di1[i][0]    ),

       .si1   ( di1[i][0]    ),

       .si2   ( di2[i][0]    ),

       .si2   ( di2[i][0]    ),

       .si3   ( di3[i][0]    ),

       .si3   ( di3[i][0]    ),

       .si4   ( di4[i][0]    ),

       .si4   ( di4[i][0]    ),

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       .li0   ( di0[i][4]    ),

       .li0   ( di0[i][4]    ),

       .li1   ( di1[i][4]    ),

       .li1   ( di1[i][4]    ),

       .li2   ( di2[i][4]    ),

       .li2   ( di2[i][4]    ),

       .li3   ( di3[i][4]    ),

       .li3   ( di3[i][4]    ),

       .li4   ( di4[i][4]    ),

       .li4   ( di4[i][4]    ),

       .soa   ( cmoa[i][0]   ),

          .soa   ( doa[i][0]    ),

       .woa   ( cmoa[i][1]   ),

          .woa   ( doa[i][1]    ),

       .noa   ( cmoa[i][2]   ),

          .noa   ( doa[i][2]    ),

       .eoa   ( cmoa[i][3]   ),

          .eoa   ( doa[i][3]    ),

       .loa   ( cmoa[i][4]   ),

          .loa   ( doa[i][4]    ),

       .soa4  ( cmoa4[i][0]  ),

          .soa4  ( doa4[i][0]   ),

       .woa4  ( cmoa4[i][1]  ),

          .woa4  ( doa4[i][1]   ),

       .noa4  ( cmoa4[i][2]  ),

          .noa4  ( doa4[i][2]   ),

       .eoa4  ( cmoa4[i][3]  ),

          .eoa4  ( doa4[i][3]   ),

       .loa4  ( cmoa4[i][4]  ),

          .loa4  ( doa4[i][4]   ),

       .wcfg  ( wcfg[i]      ),

       .wcfg  ( wcfg[i]      ),

       .ecfg  ( ecfg[i]      ),

       .ecfg  ( ecfg[i]      ),

       .lcfg  ( lcfg[i]      ),

       .lcfg  ( lcfg[i]      ),

       .scfg  ( scfg[i]      ),

       .scfg  ( scfg[i]      ),

       .ncfg  ( ncfg[i]      )

       .ncfg  ( ncfg[i]      )

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                 .nr    ( ndec  ),

                 .nr    ( ndec  ),

                 .er    ( edec  ),

                 .er    ( edec  ),

                 .lr    ( ldec  )

                 .lr    ( ldec  )

);

);

endmodule // cm

endmodule // cm

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