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module im (/*AUTOARG*/
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module im (/*AUTOARG*/
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// Outputs
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// Outputs
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do0, do1, do2, do3, deco, dia, do4,
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do0, do1, do2, do3, deco, dia, do4,
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// Inputs
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// Inputs
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di0, di1, di2, di3, deci, di4, doa, doa4
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di0, di1, di2, di3, deci, di4, doa,
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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, cms
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cms,
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`endif
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`endif
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, rst_n
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rst_n
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);
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);
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parameter MN = 2; // the number of CMs
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parameter MN = 2; // the number of CMs
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parameter NN = 2; // the number of IPs in one IM
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parameter NN = 2; // the number of IPs in one IM
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parameter DW = 8; // the data width of a single IP
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parameter DW = 8; // the data width of a single IP
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Line 45... |
// eof bits and ack lines
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// eof bits and ack lines
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][SCN-1:0] di4; // data input
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input [NN-1:0][SCN-1:0] di4; // data input
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output [NN-1:0][SCN-1:0] dia; // input ack
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output [NN-1:0][SCN-1:0] dia; // input ack
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output [MN-1:0][SCN-1:0] do4; // data output
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output [MN-1:0][SCN-1:0] do4; // data output
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input [MN-1:0][SCN-1:0] doa, doa4; // output ack
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input [MN-1:0][SCN-1:0] doa; // output ack
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`else
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`else
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input [NN-1:0] di4; // data input
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input [NN-1:0] di4; // data input
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output [NN-1:0] dia; // input ack
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output [NN-1:0] dia; // input ack
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output [MN-1:0] do4; // data output
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output [MN-1:0] do4; // data output
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input [MN-1:0] doa, doa4; // output ack
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input [MN-1:0] doa; // output ack
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`ifndef ENABLE_CRRD
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`ifndef ENABLE_CRRD
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input [MN-1:0][SN-1:0] cms; // the states from CMs
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input [MN-1:0][SN-1:0] cms; // the states from CMs
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`endif
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`endif
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