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Rev 69 Rev 70
Line 22... Line 22...
 
 
module im (/*AUTOARG*/
module im (/*AUTOARG*/
   // Outputs
   // Outputs
   do0, do1, do2, do3, deco, dia, do4,
   do0, do1, do2, do3, deco, dia, do4,
   // Inputs
   // Inputs
   di0, di1, di2, di3, deci, di4, doa, doa4
   di0, di1, di2, di3, deci, di4, doa,
`ifndef ENABLE_CRRD
`ifndef ENABLE_CRRD
   , cms
   cms,
`endif
`endif
   , rst_n
   rst_n
   );
   );
 
 
   parameter MN = 2;            // the number of CMs
   parameter MN = 2;            // the number of CMs
   parameter NN = 2;            // the number of IPs in one IM
   parameter NN = 2;            // the number of IPs in one IM
   parameter DW = 8;            // the data width of a single IP
   parameter DW = 8;            // the data width of a single IP
Line 45... Line 45...
   // eof bits and ack lines
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
`ifdef ENABLE_CHANNEL_SLICING
   input [NN-1:0][SCN-1:0]        di4; // data input
   input [NN-1:0][SCN-1:0]        di4; // data input
   output [NN-1:0][SCN-1:0]     dia; // input ack
   output [NN-1:0][SCN-1:0]     dia; // input ack
   output [MN-1:0][SCN-1:0]       do4; // data output
   output [MN-1:0][SCN-1:0]       do4; // data output
   input [MN-1:0][SCN-1:0]        doa, doa4; // output ack
   input [MN-1:0][SCN-1:0]        doa; // output ack
`else
`else
   input [NN-1:0]                di4; // data input
   input [NN-1:0]                di4; // data input
   output [NN-1:0]               dia; // input ack
   output [NN-1:0]               dia; // input ack
   output [MN-1:0]               do4; // data output
   output [MN-1:0]               do4; // data output
   input [MN-1:0]                doa, doa4; // output ack
   input [MN-1:0]                doa; // output ack
`endif // !`ifdef ENABLE_CHANNEL_SLICING
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
 
`ifndef ENABLE_CRRD
`ifndef ENABLE_CRRD
   input [MN-1:0][SN-1:0]         cms; // the states from CMs
   input [MN-1:0][SN-1:0]         cms; // the states from CMs
`endif
`endif

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