| Line 24... |
Line 24... |
05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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12/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module inp_buf (/*AUTOARG*/
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module inp_buf (/*AUTOARG*/
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// Outputs
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// Outputs
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o0, o1, o2, o3, o4, ia, arb_r,
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o0, o1, o2, o3, o4, ia, deco,
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// Inputs
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// Inputs
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry, arb_ra
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rst_n, i0, i1, i2, i3, i4, oa, addrx, addry
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);
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);
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//-------------------------- parameters ---------------------------------------//
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//-------------------------- parameters ---------------------------------------//
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter DIR = 0; // the port direction: south, west, north, east, and local
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parameter RN = 4; // the number of request outputs, must match the direction
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parameter RN = 4; // the number of request outputs, must match the direction
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| Line 54... |
Line 56... |
output [SCN-1:0] o4, ia;
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output [SCN-1:0] o4, ia;
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`else
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`else
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input i4, oa;
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input i4, oa;
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output o4, ia;
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output o4, ia;
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`endif
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`endif
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input [7:0] addrx, addry;
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input [7:0] addrx, addry; // local addresses in 1-of-4 encoding
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output [RN-1:0] arb_r;
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output [RN-1:0] deco; // the decoded routing requests
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input arb_ra;
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//-------------------------- control signals ---------------------------------------//
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//-------------------------- control signals ---------------------------------------//
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wire rten; // routing enable
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wire rten; // routing enable
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wire frame_end; // identify the end of a frame
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wire frame_end; // identify the end of a frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire x_equal; // addr x = target x
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wire x_equal; // addr x = target x
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wire rt_err; // route decoder error
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wire rt_err; // route decoder error
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wire rt_ack; // route build ack
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel
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wire [SCN-1:0] deca; // the ack for routing requests
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages
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`else
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`else
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wire rtrst; // rt decode reset
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wire deca; // the ack for routing requests
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wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
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wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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wire decan;
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genvar i, j;
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genvar i, j;
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//------------------------- pipelines ------------------------------------- //
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//------------------------- pipelines ------------------------------------- //
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generate for(i=0; i<PD; i++) begin: DP
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generate for(i=0; i<PD; i++) begin: DP
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| Line 90... |
Line 91... |
P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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//.o4 ( pd4[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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//.i4 ( pd4[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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|
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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| Line 118... |
Line 117... |
P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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//.o4 ( pd4[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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//.i4 ( pd4[i+1] ),
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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