| Line 65... |
Line 65... |
wire rta; // the ack of the dec reg pipeline stage
|
wire rta; // the ack of the dec reg pipeline stage
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wire frame_end; // identify the end of a frame
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wire frame_end; // identify the end of a frame
|
wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
|
wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
|
wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] raw_dec; // the routing decision from the comparator
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wire [5:0] xy_dec; // the routing decision of the XY routing algorithm
|
wire [4:0] xy_dec; // the routing decision of the XY routing algorithm
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire [4:0] dec_reg; // the routing decision kept by C-gates
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wire x_equal; // addr x = target x
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wire x_equal; // addr x = target x
|
wire rt_err; // route decoder error
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wire rt_err; // route decoder error
|
|
|
`ifdef ENABLE_CHANNEL_SLICING
|
`ifdef ENABLE_CHANNEL_SLICING
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| Line 80... |
Line 80... |
|
|
`else
|
`else
|
wire deca; // the ack for routing requests
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wire deca; // the ack for routing requests
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wire pda1; // the ack for the 1st pipeline stage
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wire pda1; // the ack for the 1st pipeline stage
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wire acko; // the ack from CB
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wire acko; // the ack from CB
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wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
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wire [PD:0] pd4, pda, pdan, pda4n; // data wires for the internal pipeline satges
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
wire decan;
|
wire decan;
|
|
|
genvar i, j;
|
genvar i, j;
|
|
|
| Line 109... |
Line 109... |
pipen #(.DW(1))
|
pipen #(.DW(1))
|
PEoF (
|
PEoF (
|
.d_in_a ( ),
|
.d_in_a ( ),
|
.d_out ( pd4[i][j] ),
|
.d_out ( pd4[i][j] ),
|
.d_in ( pd4[i+1][j] ),
|
.d_in ( pd4[i+1][j] ),
|
.d_out_a ( pd4an[i][j] )
|
.d_out_a ( pda4n[i][j] )
|
);
|
);
|
|
|
end // block: SC
|
end // block: SC
|
|
|
`else // !`ifdef ENABLE_CHANNEL_SLICING
|
`else // !`ifdef ENABLE_CHANNEL_SLICING
|
| Line 134... |
Line 134... |
pipen #(.DW(1))
|
pipen #(.DW(1))
|
PEoF (
|
PEoF (
|
.d_in_a ( ),
|
.d_in_a ( ),
|
.d_out ( pd4[i] ),
|
.d_out ( pd4[i] ),
|
.d_in ( pd4[i+1] ),
|
.d_in ( pd4[i+1] ),
|
.d_out_a ( pd4an[i] )
|
.d_out_a ( pda4n[i] )
|
);
|
);
|
|
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING
|
end // block: DP
|
end // block: DP
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
for(i=2; i<PD; i++) begin: DPA
|
for(i=2; i<PD; i++) begin: DPA
|
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
|
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
|
assign pd4an[i] = pdan[i];
|
assign pda4n[i] = pdan[i];
|
end
|
end
|
|
|
// in case only one pipeline stage is configured
|
// in case only one pipeline stage is configured
|
if(PD>1)
|
if(PD>1)
|
assign ia = pda[PD]|pd4[PD-1];
|
assign ia = pda[PD]|pd4[PD-1];
|
| Line 201... |
Line 201... |
// translate it into the XY dec; not QDI here as the circuit can be slow
|
// translate it into the XY dec; not QDI here as the circuit can be slow
|
assign xy_dec[1:0] = raw_dec[1:0];
|
assign xy_dec[1:0] = raw_dec[1:0];
|
assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
|
assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
|
|
|
// the decoded routing requests
|
// the decoded routing requests
|
pipen #(.DW(RN))
|
pipen #(.DW(5))
|
PDEC (
|
PDEC (
|
.d_in_a ( rta ),
|
.d_in_a ( rta ),
|
.d_out ( dec_reg ),
|
.d_out ( dec_reg ),
|
.d_in ( xy_dec ),
|
.d_in ( xy_dec ),
|
.d_out_a ( decan )
|
.d_out_a ( decan )
|
