| Line 20... |
Line 20... |
26/05/2009 Initial version. <wsong83@gmail.com>
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26/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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20/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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// the out buffer
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// the out buffer
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module outp_buf (/*AUTOARG*/
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module outp_buf (/*AUTOARG*/
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// Outputs
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// Outputs
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o0, o1, o2, o3, o4, ia,
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o0, o1, o2, o3, o4, ia, ia4,
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// Inputs
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// Inputs
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rst_n, i0, i1, i2, i3, i4, oa
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rst_n, i0, i1, i2, i3, i4, oa
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);
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);
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|
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parameter DW = 16; // the datawidth of a single virtual circuit
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parameter DW = 16; // the datawidth of a single virtual circuit
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| Line 49... |
Line 50... |
output [SCN-1:0] o4, ia;
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output [SCN-1:0] o4, ia;
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wire [SCN-1:0] ian_dly;
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wire [SCN-1:0] ian_dly;
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // internal eof and ack
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // internal eof and ack
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`else
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`else
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input i4, oa; // eof and ack
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input i4, oa; // eof and ack
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output o4, ia;
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output o4, ia, ia4;
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wire ian_dly;
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wire ian_dly;
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wire [PD:0] pd4, pda, pdan, pd4an; // internal eof and ack
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wire [PD:0] pd4, pda, pdan, pd4an; // internal eof and ack
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`endif
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`endif
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| Line 66... |
Line 67... |
P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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//.o4 ( pd4[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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//.i4 ( pd4[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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| Line 92... |
Line 91... |
P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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//.o4 ( pd4[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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//.i4 ( pd4[i+1] ),
|
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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|
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
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PEoF (
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| Line 125... |
Line 122... |
// generate the input ack, add the AND gate if lookahead pipelines are used
|
// generate the input ack, add the AND gate if lookahead pipelines are used
|
generate
|
generate
|
`ifdef ENABLE_CHANNEL_SLICING
|
`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin: SCA
|
for(j=0; j<SCN; j++) begin: SCA
|
`ifdef ENABLE_LOOKAHEAD
|
`ifdef ENABLE_LOOKAHEAD
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and ACKG (ia[j], pda[PD][j]|pd4[PD-1][j], ian_dly[j]);
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and ACKG (ia[j], pda[PD][j], ian_dly[j]);
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delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
|
delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
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`else
|
`else
|
assign ia[j] = pda[PD][j]|pd4[PD-1][j];
|
assign ia[j] = pda[PD][j];
|
`endif
|
`endif
|
|
assign ia4[j] = pd4[PD-1][j];
|
assign pdan[0][j] = (~oa[j])&rst_n;
|
assign pdan[0][j] = (~oa[j])&rst_n;
|
assign pd4an[0][j] = pdan[0][j];
|
assign pd4an[0][j] = pdan[0][j];
|
end
|
end
|
`else
|
`else
|
`ifdef ENABLE_LOOKAHEAD
|
`ifdef ENABLE_LOOKAHEAD
|
and ACKG (ia, pda[PD]|pd4[PD-1], ian_dly);
|
and ACKG (ia, pda[PD], ian_dly);
|
delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
|
delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
|
`else
|
`else
|
assign ia = pda[PD]|pd4[PD-1];
|
assign ia = pda[PD];
|
`endif
|
`endif
|
|
assign ia4 = pd4[PD-1];
|
assign pdan[0] = (~oa)&rst_n;
|
assign pdan[0] = (~oa)&rst_n;
|
assign pd4an[0] = pdan[0];
|
assign pd4an[0] = pdan[0];
|
`endif // !`ifdef ENABLE_LOOKAHEAD
|
`endif // !`ifdef ENABLE_LOOKAHEAD
|
endgenerate
|
endgenerate
|
|
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