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// Verilog model for ibctl
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// Verilog model for ibctl
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// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
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// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
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// CPU time for synthesis (host <unknown>): 0.07 seconds
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// CPU time for synthesis (host <unknown>): 0.11 seconds
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// Estimated area = 8.00
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// Estimated area = 11.00
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// The circuit is self-resetting and does not need reset pin.
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// The circuit is self-resetting and does not need reset pin.
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module ibctl_net (
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module ibctl_net (
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dec,
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dec,
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Line 26... |
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// Functions not mapped into library gates:
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// Functions not mapped into library gates:
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// ----------------------------------------
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// ----------------------------------------
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// Equation: dia = eof + do
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// Equation: dia = dia eofa' dec + eof + do
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or _U0 (dia, do, eof);
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not _U0 (_X0, eofa);
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and _U1 (_X1, dia, _X0, dec);
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or _U2 (dia, do, eof, _X1);
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// Equation: eofa = eof' eofa + doa'
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// Equation: eofa = eof' eofa + doa'
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not _U1 (_X0, doa);
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not _U3 (_X2, doa);
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not _U2 (_X1, eof);
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not _U4 (_X3, eof);
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and _U3 (_X2, _X1, eofa);
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and _U5 (_X4, _X3, eofa);
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or _U4 (eofa, _X0, _X2);
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or _U6 (eofa, _X2, _X4);
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// Equation: deca = eof' eofa + doa'
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// Equation: deca = eof' eofa + doa'
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not _U5 (_X3, doa);
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not _U7 (_X5, doa);
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not _U6 (_X4, eof);
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not _U8 (_X6, eof);
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and _U7 (_X5, _X4, eofa);
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and _U9 (_X7, _X6, eofa);
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or _U8 (deca, _X3, _X5);
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or _U10 (deca, _X5, _X7);
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// signal values at the initial state:
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// signal values at the initial state:
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// !dec !do !doa !eof !dia eofa deca
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// !dec !do !doa !eof !dia eofa deca
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endmodule
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endmodule
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