Line 1... |
Line 1... |
// Verilog model for ibctl
|
// Verilog model for ibctl
|
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
|
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
|
// CPU time for synthesis (host <unknown>): 0.07 seconds
|
// CPU time for synthesis (host <unknown>): 0.11 seconds
|
// Estimated area = 8.00
|
// Estimated area = 11.00
|
|
|
// The circuit is self-resetting and does not need reset pin.
|
// The circuit is self-resetting and does not need reset pin.
|
|
|
module ibctl_net (
|
module ibctl_net (
|
dec,
|
dec,
|
Line 26... |
Line 26... |
|
|
|
|
// Functions not mapped into library gates:
|
// Functions not mapped into library gates:
|
// ----------------------------------------
|
// ----------------------------------------
|
|
|
// Equation: dia = eof + do
|
// Equation: dia = dia eofa' dec + eof + do
|
or _U0 (dia, do, eof);
|
not _U0 (_X0, eofa);
|
|
and _U1 (_X1, dia, _X0, dec);
|
|
or _U2 (dia, do, eof, _X1);
|
|
|
// Equation: eofa = eof' eofa + doa'
|
// Equation: eofa = eof' eofa + doa'
|
not _U1 (_X0, doa);
|
not _U3 (_X2, doa);
|
not _U2 (_X1, eof);
|
not _U4 (_X3, eof);
|
and _U3 (_X2, _X1, eofa);
|
and _U5 (_X4, _X3, eofa);
|
or _U4 (eofa, _X0, _X2);
|
or _U6 (eofa, _X2, _X4);
|
|
|
// Equation: deca = eof' eofa + doa'
|
// Equation: deca = eof' eofa + doa'
|
not _U5 (_X3, doa);
|
not _U7 (_X5, doa);
|
not _U6 (_X4, eof);
|
not _U8 (_X6, eof);
|
and _U7 (_X5, _X4, eofa);
|
and _U9 (_X7, _X6, eofa);
|
or _U8 (deca, _X3, _X5);
|
or _U10 (deca, _X5, _X7);
|
|
|
|
|
// signal values at the initial state:
|
// signal values at the initial state:
|
// !dec !do !doa !eof !dia eofa deca
|
// !dec !do !doa !eof !dia eofa deca
|
endmodule
|
endmodule
|