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# Source files for the wormhole/SDM routers
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# Source files for the wormhole/SDM routers
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#
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#
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# History:
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# History:
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# 26/05/2011 Initial version. <wsong83@gmail.com>
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# 26/05/2011 Initial version. <wsong83@gmail.com>
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# 02/06/2011 Use separated comp4 file. <wsong83@gmail.com>
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# 02/06/2011 Use separated comp4 file. <wsong83@gmail.com>
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# 21/07/2011 Buffered Clos switch. <wsong83@gmail.com>
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# the common verilog source files between VC and SDM
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# the common verilog source files between VC and SDM
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analyze -format verilog ../../common/src/cell_lib.v
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analyze -format verilog ../../common/src/cell_lib.v
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analyze -format verilog ../../common/src/ctree.v
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analyze -format verilog ../../common/src/ctree.v
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analyze -format sverilog ../../common/src/dcb.v
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analyze -format sverilog ../../common/src/dcb.v
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analyze -format sverilog ../../common/src/dcb_xy.v
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analyze -format sverilog ../../common/src/dcb_xy.v
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analyze -format sverilog ../../common/src/dclos.v
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analyze -format sverilog ../../common/src/mnma.v
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analyze -format sverilog ../../common/src/mnma.v
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analyze -format sverilog ../../common/src/mrma.v
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analyze -format sverilog ../../common/src/mrma.v
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analyze -format verilog ../../common/src/mutex_arb.v
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analyze -format verilog ../../common/src/mutex_arb.v
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analyze -format sverilog ../../common/src/pipe4.v
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analyze -format sverilog ../../common/src/pipe4.v
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analyze -format verilog ../../common/src/pipen.v
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analyze -format verilog ../../common/src/ppc.v
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analyze -format sverilog ../../common/src/rcb.v
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analyze -format sverilog ../../common/src/rcb.v
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analyze -format verilog ../../common/src/tree_arb.v
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analyze -format verilog ../../common/src/tree_arb.v
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analyze -format verilog ../../common/src/comp4.v
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analyze -format verilog ../../common/src/comp4.v
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# the private code of wormhole/SDM routers
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# the private code of wormhole/SDM routers
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analyze -format sverilog ../src/clos_sch.v
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analyze -format sverilog ../../sdm/src/cm_alloc.v
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analyze -format sverilog ../src/cm_alloc.v
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analyze -format sverilog ../../sdm/src/im_alloc.v
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analyze -format sverilog ../src/im_alloc.v
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analyze -format sverilog ../src/im.v
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analyze -format sverilog ../src/cm.v
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analyze -format sverilog ../src/clos_buf.v
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analyze -format sverilog ../src/input_buf.v
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analyze -format sverilog ../src/input_buf.v
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analyze -format sverilog ../src/output_buf.v
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analyze -format sverilog ../src/output_buf.v
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analyze -format sverilog ../src/router.v
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analyze -format sverilog ../src/router.v
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analyze -format sverilog ../src/sdm_sch.v
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analyze -format sverilog ../src/subc_ctl.v
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No newline at end of file
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No newline at end of file
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