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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
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# the common verilog source files between VC and SDM
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# the common verilog source files between VC and SDM
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analyze -format verilog ../../common/src/cell_lib.v
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analyze -format verilog ../../common/src/cell_lib.v
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analyze -format verilog ../../common/src/ctree.v
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analyze -format verilog ../../common/src/ctree.v
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analyze -format sverilog ../../common/src/dcb.v
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analyze -format sverilog ../../common/src/dcb.v
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analyze -format sverilog ../../common/src/dcb_xy.v
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analyze -format sverilog ../../common/src/dcb_xy.v
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analyze -format sverilog ../../common/src/cb.v
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analyze -format sverilog ../../common/src/mnma.v
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analyze -format sverilog ../../common/src/mnma.v
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analyze -format sverilog ../../common/src/mrma.v
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analyze -format sverilog ../../common/src/mrma.v
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analyze -format verilog ../../common/src/mutex_arb.v
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analyze -format verilog ../../common/src/mutex_arb.v
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analyze -format sverilog ../../common/src/pipe4.v
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analyze -format sverilog ../../common/src/pipe4.v
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analyze -format verilog ../../common/src/pipen.v
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analyze -format verilog ../../common/src/pipen.v
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