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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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17/07/2010 Initial version. <wsong83@gmail.com>
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17/07/2010 Initial version. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module dcb (/*AUTOARG*/
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module dcb (
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// Outputs
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// Outputs
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o0, o1, o2, o3, ia, o4,
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o0, o1, o2, o3, ia, o4,
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// Inputs
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// Inputs
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i0, i1, i2, i3, oa, i4, cfg
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i0, i1, i2, i3, oa, i4, cfg
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`ifdef ENABLE_BUFFERED_CLOS
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, o4a
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`endif
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);
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);
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parameter NN = 2; // number of input ports
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parameter NN = 2; // number of input ports
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parameter MN = 3; // number of output ports
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parameter MN = 3; // number of output ports
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parameter DW = 8; // data-width of a port
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parameter DW = 8; // data-width of a port
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output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports
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output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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output [NN-1:0][SCN-1:0] ia, o4; // eof and ack
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output [NN-1:0][SCN-1:0] ia, o4; // eof and ack
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input [MN-1:0][SCN-1:0] oa, i4;
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input [MN-1:0][SCN-1:0] oa, i4;
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`ifdef ENABLE_BUFFERED_CLOS
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input [MN-1:0][SCN-1:0] oa4; // the eof ack from output buffer
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`endif
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`else
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`else
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output [NN-1:0] ia, o4; // eof and ack
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output [NN-1:0] ia, o4; // eof and ack
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input [MN-1:0] oa, i4;
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input [MN-1:0] oa, i4;
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`endif
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`endif
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Line 55... |
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wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3;
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wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4;
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wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [NN-1:0][SCN-1:0][MN-1:0] amd, am4;
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`endif
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`else
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`else
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wire [NN-1:0][MN-1:0] am, dm4;
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wire [NN-1:0][MN-1:0] am, dm4;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [NN-1:0][MN-1:0] amd, am4;
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`endif
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`endif
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`endif
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genvar i, j, k;
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genvar i, j, k;
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generate
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generate
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and A1 (dm1[i][k][j], i1[j][k], cfg[i][j]);
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and A1 (dm1[i][k][j], i1[j][k], cfg[i][j]);
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and A2 (dm2[i][k][j], i2[j][k], cfg[i][j]);
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and A2 (dm2[i][k][j], i2[j][k], cfg[i][j]);
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and A3 (dm3[i][k][j], i3[j][k], cfg[i][j]);
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and A3 (dm3[i][k][j], i3[j][k], cfg[i][j]);
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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and A4 (dm4[i][k][j], i4[j][k], cfg[i][j]);
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and A4 (dm4[i][k][j], i4[j][k], cfg[i][j]);
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`ifdef ENABLE_BUFFERED_CLOS
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and Aad (amd[j][k][i], oa[i][k], cfg[i][j]);
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c2 Aa4 (.q(am4[j][k][i]), .a0(oa4[i][k]), .a1(cfg[i][j]));
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assign am[j][k][i] = amd[j][k][i] | am4[j][k][i];
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`else
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and Aa (am[j][k][i], oa[i][k], cfg[i][j]);
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and Aa (am[j][k][i], oa[i][k], cfg[i][j]);
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`endif
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`endif
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`endif
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end
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end
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`ifndef ENABLE_CHANNEL_SLICING
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`ifndef ENABLE_CHANNEL_SLICING
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and A4 (dm4[i][j], i4[j], cfg[i][j]);
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and A4 (dm4[i][j], i4[j], cfg[i][j]);
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`ifdef ENABLE_BUFFERED_CLOS
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and Aa (amd[j][i], oa[i], cfg[i][j]);
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c2 Aa4 (.q(am4[j][i]), .a0(oa4[i]), .a1(cfg[i][j]));
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assign am[j][i] = amd[j][i] | am4[j][i];
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`else
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and Aa (am[j][i], oa[i], cfg[i][j]);
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and Aa (am[j][i], oa[i], cfg[i][j]);
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`endif
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`endif
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`endif
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end // block: IP
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end // block: IP
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end // block: EN
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end // block: EN
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endgenerate
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endgenerate
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generate
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generate
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