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History:
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History:
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17/07/2010 Initial version. <wsong83@gmail.com>
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17/07/2010 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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module dclos (/*AUTOARG*/
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module dclos (
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// Outputs
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// Outputs
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
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wia, nia, eia, lia,
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wia, nia, eia, lia,
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// Inputs
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// Inputs
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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`ifdef ENABLE_BUFFERED_CLOS
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, soa4, woa4, noa4, eoa4, loa4
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`endif
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);
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);
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parameter MN = 2; // number of CMs
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parameter MN = 2; // number of CMs
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter DW = 8; // datawidth of a single virtual circuit/port
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Line 57... |
`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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`else
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`else
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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input [NN-1:0] si4, wi4, ni4, ei4, li4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] so4, wo4, no4, eo4, lo4;
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output [NN-1:0] sia, wia, nia, eia, lia;
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output [NN-1:0] sia, wia, nia, eia, lia;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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input [NN-1:0] soa, woa, noa, eoa, loa;
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`ifdef ENABLE_BUFFERED_CLOS
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input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
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`endif
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
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input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs
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// configuration for CMs
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// configuration for CMs
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input [MN-1:0][1:0] scfg, ncfg;
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input [MN-1:0][1:0] scfg, ncfg;
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Line 85... |
wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3;
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wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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`endif
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`else
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`else
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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`endif
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`endif
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`endif
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// input of CMs
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// input of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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Line 108... |
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// output of CMs
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// output of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
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wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0][SCN-1:0] cmoa4;
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`endif
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`else
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`else
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wire [MN-1:0][4:0] cmo4, cmoa;
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wire [MN-1:0][4:0] cmo4, cmoa;
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][4:0] cmoa4;
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`endif
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`endif
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`endif
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genvar i,j,k;
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genvar i,j,k;
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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dcb #(.NN(NN), .MN(MN), .DW(DW))
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