OpenCores

Rev 62	Rev 64
Line 134...	Line 134...
`.i1 ( si1 ),`	`.i1 ( si1 ),`
`.i2 ( si2 ),`	`.i2 ( si2 ),`
`.i3 ( si3 ),`	`.i3 ( si3 ),`
`.i4 ( si4 ),`	`.i4 ( si4 ),`
`.oa ( imosa ),`	`.oa ( imosa ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.oa4 ( imosa4 ),`
	`endif
`.cfg ( imcfg[0] )`	`.cfg ( imcfg[0] )`
`);`	`);`

`dcb #(.NN(NN), .MN(MN), .DW(DW))`	`dcb #(.NN(NN), .MN(MN), .DW(DW))`
`WIM (`	`WIM (`
Line 151...	Line 154...
`.i1 ( wi1 ),`	`.i1 ( wi1 ),`
`.i2 ( wi2 ),`	`.i2 ( wi2 ),`
`.i3 ( wi3 ),`	`.i3 ( wi3 ),`
`.i4 ( wi4 ),`	`.i4 ( wi4 ),`
`.oa ( imowa ),`	`.oa ( imowa ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.oa4 ( imowa4 ),`
	`endif
`.cfg ( imcfg[1] )`	`.cfg ( imcfg[1] )`
`);`	`);`

`dcb #(.NN(NN), .MN(MN), .DW(DW))`	`dcb #(.NN(NN), .MN(MN), .DW(DW))`
`NIM (`	`NIM (`
Line 168...	Line 174...
`.i1 ( ni1 ),`	`.i1 ( ni1 ),`
`.i2 ( ni2 ),`	`.i2 ( ni2 ),`
`.i3 ( ni3 ),`	`.i3 ( ni3 ),`
`.i4 ( ni4 ),`	`.i4 ( ni4 ),`
`.oa ( imona ),`	`.oa ( imona ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.oa4 ( imona4 ),`
	`endif
`.cfg ( imcfg[2] )`	`.cfg ( imcfg[2] )`
`);`	`);`

`dcb #(.NN(NN), .MN(MN), .DW(DW))`	`dcb #(.NN(NN), .MN(MN), .DW(DW))`
`EIM (`	`EIM (`
Line 185...	Line 194...
`.i1 ( ei1 ),`	`.i1 ( ei1 ),`
`.i2 ( ei2 ),`	`.i2 ( ei2 ),`
`.i3 ( ei3 ),`	`.i3 ( ei3 ),`
`.i4 ( ei4 ),`	`.i4 ( ei4 ),`
`.oa ( imoea ),`	`.oa ( imoea ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.oa4 ( imoea4 ),`
	`endif
`.cfg ( imcfg[3] )`	`.cfg ( imcfg[3] )`
`);`	`);`

`dcb #(.NN(NN), .MN(MN), .DW(DW))`	`dcb #(.NN(NN), .MN(MN), .DW(DW))`
`LIM (`	`LIM (`
Line 202...	Line 214...
`.i1 ( li1 ),`	`.i1 ( li1 ),`
`.i2 ( li2 ),`	`.i2 ( li2 ),`
`.i3 ( li3 ),`	`.i3 ( li3 ),`
`.i4 ( li4 ),`	`.i4 ( li4 ),`
`.oa ( imola ),`	`.oa ( imola ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.oa4 ( imola4 ),`
	`endif
`.cfg ( imcfg[4] )`	`.cfg ( imcfg[4] )`
`);`	`);`

`generate for(i=0; i<MN; i++) begin: IMSHF`	`generate for(i=0; i<MN; i++) begin: IMSHF`
	`ifdef ENABLE_BUFFERED_CLOS
	`// the buffer stage between IM and CM`
	`ifdef ENABLE_CHANNEL_SLICING
	`for(j=0; j<SCN; j++) begin:SC`
	`pipe4 #(.DW(2))`
	`P (`
	`.o0 ( cmi0[i][0] ),`
	`.o1 ( cmi1[i][0] ),`
	`.o2 ( cmi2[i][0] ),`
	`.o3 ( cmi3[i][0] ),`
	`.ia ( imosa[i] ),`
	`.i0 ( imos0[i] ),`
	`.i1 ( imos1[i] ),`
	`.i2 ( imos3[i] ),`
	`.i3 ( imos4[i] ),`


	`else
`// shuffle the interconnects between IMs and CMs`	`// shuffle the interconnects between IMs and CMs`
`assign cmi0[i][0] = imos0[i];`	`assign cmi0[i][0] = imos0[i];`
`assign cmi1[i][0] = imos1[i];`	`assign cmi1[i][0] = imos1[i];`
`assign cmi2[i][0] = imos2[i];`	`assign cmi2[i][0] = imos2[i];`
`assign cmi3[i][0] = imos3[i];`	`assign cmi3[i][0] = imos3[i];`
Line 241...	Line 274...
`assign cmi1[i][4] = imol1[i];`	`assign cmi1[i][4] = imol1[i];`
`assign cmi2[i][4] = imol2[i];`	`assign cmi2[i][4] = imol2[i];`
`assign cmi3[i][4] = imol3[i];`	`assign cmi3[i][4] = imol3[i];`
`assign cmi4[i][4] = imol4[i];`	`assign cmi4[i][4] = imol4[i];`
`assign imola[i] = cmia[i][4];`	`assign imola[i] = cmia[i][4];`
	`endif // !`ifdef ENABLE_BUFFERED_CLOS

`// CM modules`	`// CM modules`
`dcb_xy #(.VCN(1), .VCW(DW))`	`dcb_xy #(.VCN(1), .VCW(DW))`
`CM (`	`CM (`
`.sia ( cmia[i][0] ),`	`.sia ( cmia[i][0] ),`
Line 305...	Line 339...
`.soa ( cmoa[i][0] ),`	`.soa ( cmoa[i][0] ),`
`.woa ( cmoa[i][1] ),`	`.woa ( cmoa[i][1] ),`
`.noa ( cmoa[i][2] ),`	`.noa ( cmoa[i][2] ),`
`.eoa ( cmoa[i][3] ),`	`.eoa ( cmoa[i][3] ),`
`.loa ( cmoa[i][4] ),`	`.loa ( cmoa[i][4] ),`
	`ifdef ENABLE_BUFFERED_CLOS
	`.soa4 ( cmoa4[i][0] ),`
	`.woa4 ( cmoa4[i][1] ),`
	`.noa4 ( cmoa4[i][2] ),`
	`.eoa4 ( cmoa4[i][3] ),`
	`.loa4 ( cmoa4[i][4] ),`
	`endif
`.wcfg ( wcfg[i] ),`	`.wcfg ( wcfg[i] ),`
`.ecfg ( ecfg[i] ),`	`.ecfg ( ecfg[i] ),`
`.lcfg ( lcfg[i] ),`	`.lcfg ( lcfg[i] ),`
`.scfg ( scfg[i] ),`	`.scfg ( scfg[i] ),`
`.ncfg ( ncfg[i] )`	`.ncfg ( ncfg[i] )`
Line 347...	Line 388...
`assign lo1[i] = cmo1[i][4];`	`assign lo1[i] = cmo1[i][4];`
`assign lo2[i] = cmo2[i][4];`	`assign lo2[i] = cmo2[i][4];`
`assign lo3[i] = cmo3[i][4];`	`assign lo3[i] = cmo3[i][4];`
`assign lo4[i] = cmo4[i][4];`	`assign lo4[i] = cmo4[i][4];`
`assign cmoa[i][4] = loa[i];`	`assign cmoa[i][4] = loa[i];`

	`ifdef ENABLE_BUFFERED_CLOS
	`assign cmoa4[i][0] = soa4[i];`
	`assign cmoa4[i][1] = woa4[i];`
	`assign cmoa4[i][2] = noa4[i];`
	`assign cmoa4[i][3] = eoa4[i];`
	`assign cmoa4[i][4] = loa4[i];`
	`endif
`end // block: IMSHF`	`end // block: IMSHF`

`endgenerate`	`endgenerate`

Line 134...

       .i1  ( si1      ),

       .i1  ( si1      ),

       .i2  ( si2      ),

       .i2  ( si2      ),

       .i3  ( si3      ),

       .i3  ( si3      ),

       .i4  ( si4      ),

       .i4  ( si4      ),

       .oa  ( imosa    ),

       .oa  ( imosa    ),

`ifdef ENABLE_BUFFERED_CLOS

        .oa4 ( imosa4   ),

`endif

       .cfg ( imcfg[0] )

       .cfg ( imcfg[0] )

);

);

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   WIM (

   WIM (

Line 151...

Line 154...

       .i1  ( wi1      ),

       .i1  ( wi1      ),

       .i2  ( wi2      ),

       .i2  ( wi2      ),

       .i3  ( wi3      ),

       .i3  ( wi3      ),

       .i4  ( wi4      ),

       .i4  ( wi4      ),

       .oa  ( imowa    ),

       .oa  ( imowa    ),

`ifdef ENABLE_BUFFERED_CLOS

        .oa4 ( imowa4   ),

`endif

       .cfg ( imcfg[1] )

       .cfg ( imcfg[1] )

);

);

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   NIM (

   NIM (

Line 168...

Line 174...

       .i1  ( ni1      ),

       .i1  ( ni1      ),

       .i2  ( ni2      ),

       .i2  ( ni2      ),

       .i3  ( ni3      ),

       .i3  ( ni3      ),

       .i4  ( ni4      ),

       .i4  ( ni4      ),

       .oa  ( imona    ),

       .oa  ( imona    ),

`ifdef ENABLE_BUFFERED_CLOS

        .oa4 ( imona4   ),

`endif

       .cfg ( imcfg[2] )

       .cfg ( imcfg[2] )

);

);

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   EIM (

   EIM (

Line 185...

Line 194...

       .i1  ( ei1      ),

       .i1  ( ei1      ),

       .i2  ( ei2      ),

       .i2  ( ei2      ),

       .i3  ( ei3      ),

       .i3  ( ei3      ),

       .i4  ( ei4      ),

       .i4  ( ei4      ),

       .oa  ( imoea    ),

       .oa  ( imoea    ),

`ifdef ENABLE_BUFFERED_CLOS

        .oa4 ( imoea4   ),

`endif

       .cfg ( imcfg[3] )

       .cfg ( imcfg[3] )

);

);

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   dcb #(.NN(NN), .MN(MN), .DW(DW))

   LIM (

   LIM (

Line 202...

Line 214...

       .i1  ( li1      ),

       .i1  ( li1      ),

       .i2  ( li2      ),

       .i2  ( li2      ),

       .i3  ( li3      ),

       .i3  ( li3      ),

       .i4  ( li4      ),

       .i4  ( li4      ),

       .oa  ( imola    ),

       .oa  ( imola    ),

`ifdef ENABLE_BUFFERED_CLOS

        .oa4 ( imola4   ),

`endif

       .cfg ( imcfg[4] )

       .cfg ( imcfg[4] )

);

);

   generate for(i=0; i<MN; i++) begin: IMSHF

   generate for(i=0; i<MN; i++) begin: IMSHF

`ifdef ENABLE_BUFFERED_CLOS

      // the buffer stage between IM and CM

 `ifdef ENABLE_CHANNEL_SLICING

      for(j=0; j<SCN; j++) begin:SC

         pipe4 #(.DW(2))

P (

            .o0 ( cmi0[i][0]  ),

            .o1 ( cmi1[i][0]  ),

            .o2 ( cmi2[i][0]  ),

            .o3 ( cmi3[i][0]  ),

            .ia ( imosa[i]    ),

            .i0 ( imos0[i]    ),

            .i1 ( imos1[i]    ),

            .i2 ( imos3[i]    ),

            .i3 ( imos4[i]    ),

`else

      // shuffle the interconnects between IMs and CMs

      // shuffle the interconnects between IMs and CMs

      assign cmi0[i][0] = imos0[i];

      assign cmi0[i][0] = imos0[i];

      assign cmi1[i][0] = imos1[i];

      assign cmi1[i][0] = imos1[i];

      assign cmi2[i][0] = imos2[i];

      assign cmi2[i][0] = imos2[i];

      assign cmi3[i][0] = imos3[i];

      assign cmi3[i][0] = imos3[i];

Line 241...

Line 274...

      assign cmi1[i][4] = imol1[i];

      assign cmi1[i][4] = imol1[i];

      assign cmi2[i][4] = imol2[i];

      assign cmi2[i][4] = imol2[i];

      assign cmi3[i][4] = imol3[i];

      assign cmi3[i][4] = imol3[i];

      assign cmi4[i][4] = imol4[i];

      assign cmi4[i][4] = imol4[i];

      assign imola[i] = cmia[i][4];

      assign imola[i] = cmia[i][4];

`endif // !`ifdef ENABLE_BUFFERED_CLOS

      // CM modules

      // CM modules

      dcb_xy #(.VCN(1), .VCW(DW))

      dcb_xy #(.VCN(1), .VCW(DW))

      CM (

      CM (

          .sia   ( cmia[i][0]   ),

          .sia   ( cmia[i][0]   ),

Line 305...

Line 339...

          .soa   ( cmoa[i][0]   ),

          .soa   ( cmoa[i][0]   ),

          .woa   ( cmoa[i][1]   ),

          .woa   ( cmoa[i][1]   ),

          .noa   ( cmoa[i][2]   ),

          .noa   ( cmoa[i][2]   ),

          .eoa   ( cmoa[i][3]   ),

          .eoa   ( cmoa[i][3]   ),

          .loa   ( cmoa[i][4]   ),

          .loa   ( cmoa[i][4]   ),

`ifdef ENABLE_BUFFERED_CLOS

          .soa4  ( cmoa4[i][0]  ),

          .woa4  ( cmoa4[i][1]  ),

          .noa4  ( cmoa4[i][2]  ),

          .eoa4  ( cmoa4[i][3]  ),

          .loa4  ( cmoa4[i][4]  ),

`endif

          .wcfg  ( wcfg[i]      ),

          .wcfg  ( wcfg[i]      ),

          .ecfg  ( ecfg[i]      ),

          .ecfg  ( ecfg[i]      ),

          .lcfg  ( lcfg[i]      ),

          .lcfg  ( lcfg[i]      ),

          .scfg  ( scfg[i]      ),

          .scfg  ( scfg[i]      ),

          .ncfg  ( ncfg[i]      )

          .ncfg  ( ncfg[i]      )

Line 347...

Line 388...

      assign lo1[i] = cmo1[i][4];

      assign lo1[i] = cmo1[i][4];

      assign lo2[i] = cmo2[i][4];

      assign lo2[i] = cmo2[i][4];

      assign lo3[i] = cmo3[i][4];

      assign lo3[i] = cmo3[i][4];

      assign lo4[i] = cmo4[i][4];

      assign lo4[i] = cmo4[i][4];

      assign cmoa[i][4] = loa[i];

      assign cmoa[i][4] = loa[i];

`ifdef ENABLE_BUFFERED_CLOS

      assign cmoa4[i][0] = soa4[i];

      assign cmoa4[i][1] = woa4[i];

      assign cmoa4[i][2] = noa4[i];

      assign cmoa4[i][3] = eoa4[i];

      assign cmoa4[i][4] = loa4[i];

`endif

   end // block: IMSHF

   end // block: IMSHF

   endgenerate

   endgenerate

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[/] [async_sdm_noc/] [branches/] [clos_opt/] [common/] [src/] [dclos.v] - Diff between revs 62 and 64