| Line 33... |
Line 33... |
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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, soa4, woa4, noa4, eoa4, loa4
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, soa4, woa4, noa4, eoa4, loa4
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`endif
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`endif
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, rst_n
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);
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);
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|
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parameter MN = 2; // number of CMs
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parameter MN = 2; // number of CMs
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits
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parameter DW = 8; // datawidth of a single virtual circuit/port
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parameter DW = 8; // datawidth of a single virtual circuit/port
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| Line 76... |
Line 77... |
// configuration for CMs
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// configuration for CMs
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input [MN-1:0][1:0] scfg, ncfg;
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input [MN-1:0][1:0] scfg, ncfg;
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input [MN-1:0][3:0] wcfg, ecfg, lcfg;
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input [MN-1:0][3:0] wcfg, ecfg, lcfg;
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// no OMs
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// no OMs
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|
|
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input rst_n; // globale active low reset
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// output of IMs
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// output of IMs
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wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3;
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wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3;
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wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3;
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wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3;
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wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3;
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wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3;
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wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3;
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| Line 87... |
Line 90... |
`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0][SCN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
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wire [MN-1:0][SCN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
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`endif
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`endif
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`else
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`else
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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wire [MN-1:0] imosa, imowa, imona, imoea, imola;
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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wire [MN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca;
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wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4;
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wire [MN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan;
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`endif
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`endif
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`endif
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`endif
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// input of CMs
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// input of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
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wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia;
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`ifdef ENABLE_BUFFERED_CLOS
|
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wire [MN-1:0][4:0][SCN-1:0] cmian;
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`endif
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`else
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`else
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wire [MN-1:0][4:0] cmi4, cmia;
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wire [MN-1:0][4:0] cmi4, cmia;
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`ifdef ENABLE_BUFFERED_CLOS
|
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wire [MN-1:0][4:0] cmian;
|
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`endif
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`endif
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`endif
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// output of CMs
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// output of CMs
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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| Line 224... |
Line 237... |
|
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generate for(i=0; i<MN; i++) begin: IMSHF
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generate for(i=0; i<MN; i++) begin: IMSHF
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`ifdef ENABLE_BUFFERED_CLOS
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`ifdef ENABLE_BUFFERED_CLOS
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// the buffer stage between IM and CM
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// the buffer stage between IM and CM
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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for(j=0; j<SCN; j++) begin:SC
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for(j=0; j<SCN; j++) begin:SC_S
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pipe4 #(.DW(2))
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pipe4 #(.DW(2))
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P (
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P (
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.o0 ( cmi0[i][0] ),
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.o0 ( cmi0[i][0] ),
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.o1 ( cmi1[i][0] ),
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.o1 ( cmi1[i][0] ),
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.o2 ( cmi2[i][0] ),
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.o2 ( cmi2[i][0] ),
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| Line 241... |
Line 254... |
.oa ( cmian[i][0] )
|
.oa ( cmian[i][0] )
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);
|
);
|
|
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pipen #(.DW(1))
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pipen #(.DW(1))
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PEoF (
|
PEoF (
|
.d_in_a ( imosa4[i] ),
|
.d_in_a ( ), // imosa4[i] ),
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.d_out ( cmi4[i][0] ),
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.d_out ( cmi4[i][0] ),
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.d_in ( imos4[i] ),
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.d_in ( imos4[i] ),
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.d_out_a ( cmian[i][0] ),
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.d_out_a ( imoseofan[i] ),
|
);
|
);
|
|
|
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ppc PCTL (
|
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.deca ( imosdeca[i] ),
|
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.dia ( imosa4[i] ),
|
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.eof ( cmi4[i][0] ),
|
|
.doa ( cmia[i][0] ),
|
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.dec (
|
|
);
|
|
|
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assign cmian[i][0] = (~cmia[i][0])&rst_n;
|
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assign imoseofan[i] = (imosdeca[i])&rst_n;
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end // block: SC
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|
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pipen #(.DW(4))
|
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S_PDIR (
|
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.d_in_a (
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|
|
|
|
|
|
|
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`else
|
`else
|
// shuffle the interconnects between IMs and CMs
|
// shuffle the interconnects between IMs and CMs
|
assign cmi0[i][0] = imos0[i];
|
assign cmi0[i][0] = imos0[i];
|
