| Line 23... |
Line 23... |
History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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24/05/2011 Clean up for opensource. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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| Line 71... |
Line 71... |
wire rt_err; // route decoder error
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wire rt_err; // route decoder error
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wire rt_ack; // route build ack
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wire rt_ack; // route build ack
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel
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wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel
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wire [PD:0][SCN-1:0] pd4, pda, pdan; // data wires for the internal pipeline stages
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages
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`else
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`else
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wire rtrst; // rt decode reset
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wire rtrst; // rt decode reset
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wire [PD:0] pd4, pda, pdan; // data wires for the internal pipeline satges
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wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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genvar i, j;
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genvar i, j;
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//------------------------- pipelines ------------------------------------- //
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//------------------------- pipelines ------------------------------------- //
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| Line 90... |
Line 90... |
P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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.o4 ( pd4[i][j] ),
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//.o4 ( pd4[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i4 ( pd4[i+1][j] ),
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//.i4 ( pd4[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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pipen #(.DW(1))
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PEoF (
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.d_in_a ( ),
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.d_out ( pd4[i][j] ),
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.d_in ( pd4[i+1][j] ),
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.d_out_a ( pd4an[i][j] )
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);
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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pipe4 #(.DW(DW))
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pipe4 #(.DW(DW))
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P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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.o4 ( pd4[i] ),
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//.o4 ( pd4[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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.i4 ( pd4[i+1] ),
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//.i4 ( pd4[i+1] ),
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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pipen #(.DW(1))
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PEoF (
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.d_in_a ( ),
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.d_out ( pd4[i] ),
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.d_in ( pd4[i+1] ),
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.d_out_a ( pd4an[i] )
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);
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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end // block: DP
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end // block: DP
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endgenerate
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endgenerate
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generate for(i=1; i<PD; i++) begin: DPA
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generate for(i=1; i<PD; i++) begin: DPA
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
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assign pd4an[i] = pdan[i];
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end
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end
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endgenerate
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endgenerate
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assign ia = pda[PD]|pd4[PD-1];
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assign ia = pda[PD]|pd4[PD-1];
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assign pd0[PD] = i0;
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assign pd0[PD] = i0;
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| Line 208... |
Line 228... |
.eof ( pd4[0][j] ),
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.eof ( pd4[0][j] ),
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.rt_ra ( rt_ack ),
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.rt_ra ( rt_ack ),
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.rt_err ( rt_err ),
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.rt_err ( rt_err ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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assign pd4an[0][j] = pdan[0][j];
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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subc_ctl SCH_C (
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subc_ctl SCH_C (
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.nack ( pdan[0] ),
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.nack ( pdan[0] ),
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.rt_rst ( rtrst ),
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.rt_rst ( rtrst ),
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| Line 220... |
Line 241... |
.eof ( pd4[0] ),
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.eof ( pd4[0] ),
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.rt_ra ( rt_ack ),
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.rt_ra ( rt_ack ),
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.rt_err ( rt_err ),
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.rt_err ( rt_err ),
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.rst_n ( rst_n )
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.rst_n ( rst_n )
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);
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);
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assign pd4an[0] = pdan[0];
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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// the router controller part
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// the router controller part
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assign rten = ~rt_ack;
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assign rten = ~rt_ack;
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assign frame_end = &rtrst;
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assign frame_end = &rtrst;
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