| Line 19... |
Line 19... |
History:
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History:
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26/05/2009 Initial version. <wsong83@gmail.com>
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26/05/2009 Initial version. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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| Line 45... |
Line 46... |
wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
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`ifdef ENABLE_CHANNEL_SLICING
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`ifdef ENABLE_CHANNEL_SLICING
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input [SCN-1:0] i4, oa; // eof and ack
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input [SCN-1:0] i4, oa; // eof and ack
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output [SCN-1:0] o4, ia;
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output [SCN-1:0] o4, ia;
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wire [SCN-1:0] ian_dly;
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wire [SCN-1:0] ian_dly;
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wire [PD:0][SCN-1:0] pd4, pda, pdan; // internal eof and ack
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wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // internal eof and ack
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`else
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`else
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input i4, oa; // eof and ack
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input i4, oa; // eof and ack
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output o4, ia;
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output o4, ia;
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wire ian_dly;
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wire ian_dly;
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wire [PD:0] pd4, pda, pdan; // internal eof and ack
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wire [PD:0] pd4, pda, pdan, pd4an; // internal eof and ack
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`endif
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`endif
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//-------------------------- pipeline ---------------------------------------//
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//-------------------------- pipeline ---------------------------------------//
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genvar i,j;
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genvar i,j;
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| Line 65... |
Line 66... |
P (
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P (
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.o0 ( pd0[i][j] ),
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.o0 ( pd0[i][j] ),
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.o1 ( pd1[i][j] ),
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.o1 ( pd1[i][j] ),
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.o2 ( pd2[i][j] ),
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.o2 ( pd2[i][j] ),
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.o3 ( pd3[i][j] ),
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.o3 ( pd3[i][j] ),
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.o4 ( pd4[i][j] ),
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//.o4 ( pd4[i][j] ),
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.ia ( pda[i+1][j] ),
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.ia ( pda[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i0 ( pd0[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i1 ( pd1[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i2 ( pd2[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i3 ( pd3[i+1][j] ),
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.i4 ( pd4[i+1][j] ),
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//.i4 ( pd4[i+1][j] ),
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.oa ( pdan[i][j] )
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.oa ( pdan[i][j] )
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);
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);
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pipen #(.DW(1))
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PEoF (
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.d_in_a ( ),
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.d_out ( pd4[i][j] ),
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.d_in ( pd4[i+1][j] ),
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.d_out_a ( pd4an[i][j] )
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);
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end // block: SC
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end // block: SC
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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`else // !`ifdef ENABLE_CHANNEL_SLICING
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pipe4 #(.DW(DW))
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pipe4 #(.DW(DW))
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P (
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P (
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.o0 ( pd0[i] ),
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.o0 ( pd0[i] ),
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.o1 ( pd1[i] ),
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.o1 ( pd1[i] ),
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.o2 ( pd2[i] ),
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.o2 ( pd2[i] ),
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.o3 ( pd3[i] ),
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.o3 ( pd3[i] ),
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.o4 ( pd4[i] ),
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//.o4 ( pd4[i] ),
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.ia ( pda[i+1] ),
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.ia ( pda[i+1] ),
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.i0 ( pd0[i+1] ),
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.i0 ( pd0[i+1] ),
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.i1 ( pd1[i+1] ),
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.i1 ( pd1[i+1] ),
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.i2 ( pd2[i+1] ),
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.i2 ( pd2[i+1] ),
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.i3 ( pd3[i+1] ),
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.i3 ( pd3[i+1] ),
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.i4 ( pd4[i+1] ),
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//.i4 ( pd4[i+1] ),
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.oa ( pdan[i] )
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.oa ( pdan[i] )
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);
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);
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pipen #(.DW(1))
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PEoF (
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.d_in_a ( ),
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.d_out ( pd4[i] ),
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.d_in ( pd4[i+1] ),
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.d_out_a ( pd4an[i] )
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);
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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end // block: DP
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end // block: DP
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endgenerate
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endgenerate
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// generate the ack lines for data pipelines
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// generate the ack lines for data pipelines
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| Line 113... |
Line 131... |
delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
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delay DLY ( .q(ian_dly[j]), .a(pdan[PD-1][j]));
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`else
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`else
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assign ia[j] = pda[PD][j]|pd4[PD-1][j];
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assign ia[j] = pda[PD][j]|pd4[PD-1][j];
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`endif
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`endif
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assign pdan[0][j] = (~oa[j])&rst_n;
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assign pdan[0][j] = (~oa[j])&rst_n;
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assign pd4an[0][j] = pdan[0][j];
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end
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end
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`else
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`else
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`ifdef ENABLE_LOOKAHEAD
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`ifdef ENABLE_LOOKAHEAD
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and ACKG (ia, pda[PD]|pd4[PD-1], ian_dly);
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and ACKG (ia, pda[PD]|pd4[PD-1], ian_dly);
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delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
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delay DLY ( .q(ian_dly), .a(pdan[PD-1]));
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`else
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`else
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assign ia = pda[PD]|pd4[PD-1];
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assign ia = pda[PD]|pd4[PD-1];
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`endif
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`endif
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assign pdan[0] = (~oa)&rst_n;
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assign pdan[0] = (~oa)&rst_n;
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assign pd4an[0] = pdan[0];
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`endif // !`ifdef ENABLE_LOOKAHEAD
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`endif // !`ifdef ENABLE_LOOKAHEAD
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endgenerate
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endgenerate
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// name change
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// name change
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assign pd0[PD] = i0;
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assign pd0[PD] = i0;
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