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Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
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Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
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Version: 0.1
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Version: 0.2
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On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
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On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
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current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
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current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
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Compared with synchronous NoCs, asynchronous NoCs have following benefits:
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Compared with synchronous NoCs, asynchronous NoCs have following benefits:
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* Tolerance to all kinds of delay variations caused by process, power and temperature
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* Tolerance to all kinds of delay variations caused by process, power and temperature
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direction.
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direction.
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Features:
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Features:
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* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
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* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
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* The dimension order routing (XY routing)
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* The dimension order routing (XY routing)
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* Available flow control methods: wormhole, SDM
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* Available flow control methods: wormhole, SDM, VC
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* Reconfigurable number of virtual circuits, buffer size, data width
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* Reconfigurable number of virtual circuits, buffer size, data width
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* Fully synthesizable router implementation
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* Fully synthesizable router implementation
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* SystemC testbench provided
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* SystemC testbench provided
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Languages:
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Languages:
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|- sim simulation run dir
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|- sim simulation run dir
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|- src HDL
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|- src HDL
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|- syn synthesis run dir
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|- syn synthesis run dir
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\- script synthesis script
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\- script synthesis script
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\- tb test bench
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\- tb test bench
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* vc VC router (ongoing)
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* vc VC router deign
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\- define.v HDL configure file
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|- define.h test bench configuration
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|- sim simulation run dir
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|- src HDL
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|- syn synthesis run dir
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\- script synthesis script
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\- tb test bench
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How to run:
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How to run:
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* to synthesize a router
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* to synthesize a router
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1. set up your design compiler enviornment and your cell library.
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1. set up your design compiler enviornment and your cell library.
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2. modify the "define.v" configuration file for the strcture your want.
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2. modify the "define.v" configuration file for the strcture your want.
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"throughput.ana":
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"throughput.ana":
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{simulation time in ps} TAB {throughput in bytes}
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{simulation time in ps} TAB {throughput in bytes}
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"delay.ana":
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"delay.ana":
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{simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
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{simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
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* The process of synthesize and simulate the VC router is similar to the procedure of
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the wormhole/SDM router.
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For any questions and bug reports,
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For any questions and bug reports,
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please email to Wei Song from wsong83@gmail.com
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please email to Wei Song from wsong83@gmail.com
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Wei Song
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Wei Song
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01/06/2011
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08/06/2011
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