OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [init/] [README] - Diff between revs 36 and 49

Show entire file | Details | Blame | View Log

Rev 36 Rev 49
Line 1... Line 1...
 
 
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
 
 
Version: 0.1
Version: 0.2
 
 
On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
Compared with synchronous NoCs, asynchronous NoCs have following benefits:
Compared with synchronous NoCs, asynchronous NoCs have following benefits:
  * Tolerance to all kinds of delay variations caused by process, power and temperature
  * Tolerance to all kinds of delay variations caused by process, power and temperature
Line 24... Line 24...
direction.
direction.
 
 
Features:
Features:
  * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
  * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
  * The dimension order routing (XY routing)
  * The dimension order routing (XY routing)
  * Available flow control methods: wormhole, SDM
  * Available flow control methods: wormhole, SDM, VC
  * Reconfigurable number of virtual circuits, buffer size, data width
  * Reconfigurable number of virtual circuits, buffer size, data width
  * Fully synthesizable router implementation
  * Fully synthesizable router implementation
  * SystemC testbench provided
  * SystemC testbench provided
 
 
Languages:
Languages:
Line 53... Line 53...
   |- sim                               simulation run dir
   |- sim                               simulation run dir
   |- src                               HDL
   |- src                               HDL
   |- syn                               synthesis run dir
   |- syn                               synthesis run dir
    \- script                           synthesis script
    \- script                           synthesis script
   \- tb                                test bench
   \- tb                                test bench
  * vc                                  VC router (ongoing)
  * vc                                  VC router deign
 
   \- define.v                          HDL configure file
 
   |- define.h                          test bench configuration
 
   |- sim                               simulation run dir
 
   |- src                               HDL
 
   |- syn                               synthesis run dir
 
    \- script                           synthesis script
 
   \- tb                                test bench
 
 
How to run:
How to run:
  * to synthesize a router
  * to synthesize a router
    1. set up your design compiler enviornment and your cell library.
    1. set up your design compiler enviornment and your cell library.
    2. modify the "define.v" configuration file for the strcture your want.
    2. modify the "define.v" configuration file for the strcture your want.
Line 93... Line 100...
       "throughput.ana":
       "throughput.ana":
         {simulation time in ps} TAB {throughput in bytes}
         {simulation time in ps} TAB {throughput in bytes}
       "delay.ana":
       "delay.ana":
         {simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
         {simulation time in ps} TAB {avg. frame latency} TAB {avg. path setup delay}
 
 
 
  * The process of synthesize and simulate the VC router is similar to the procedure of
 
    the wormhole/SDM router.
 
 
For any questions and bug reports,
For any questions and bug reports,
    please email to Wei Song from wsong83@gmail.com
    please email to Wei Song from wsong83@gmail.com
 
 
Wei Song
Wei Song
01/06/2011
08/06/2011
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.