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[/] [async_sdm_noc/] [branches/] [init/] [common/] [script/] [cell_constraint.tcl] - Diff between revs 24 and 26

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Rev 24 Rev 26
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# 
# 
# History:
# History:
# 03/07/2009  Initial version. <wsong83@gmail.com>
# 03/07/2009  Initial version. <wsong83@gmail.com>
# 21/05/2011  Change to the Nangate cell library. <wsong83@gmail.com>
# 21/05/2011  Change to the Nangate cell library. <wsong83@gmail.com>
 
 
set_dont_touch mutex
set_dont_touch mutex2
set_dont_touch delay
set_dont_touch delay
 
# It is not a problem if there is no delay cells in the design.
 
 
uniquify -force
uniquify -force
 
 
# C-gates on control path
# C-gates on control path
foreach_in_collection celln  [get_references -hierarchical c2_*] {
foreach_in_collection celln  [get_references -hierarchical c2_*] {
Line 36... Line 37...
 
 
# c2n gates
# c2n gates
foreach_in_collection celln  [get_references -hierarchical c2n_*] {
foreach_in_collection celln  [get_references -hierarchical c2n_*] {
    set_disable_timing [get_object_name $celln]/U1 -from B -to Z
    set_disable_timing [get_object_name $celln]/U1 -from B -to Z
}
}
 
# It is not a problem if there is no c2n cells in the design.
 
 
# c2p gates
# c2p gates
foreach_in_collection celln  [get_references -hierarchical c2p_*] {
foreach_in_collection celln  [get_references -hierarchical c2p_*] {
    set_disable_timing [get_object_name $celln]/U1 -from B -to O
    set_disable_timing [get_object_name $celln]/U1 -from B -to Z
}
}
 
# It is not a problem if there is no c2p cells in the design.
 
 
# mutex gates
# mutex gates
foreach_in_collection celln  [get_references -hierarchical mutex_*] {
foreach_in_collection celln  [get_references -hierarchical mutex2_*] {
    set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
    set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN
    set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
    set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN
    set_dont_touch [get_object_name $celln]/U2
    set_dont_touch [get_object_name $celln]/U2
    set_dont_touch [get_object_name $celln]/U3
    set_dont_touch [get_object_name $celln]/U3
}
}
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# c2p1 gates
# c2p1 gates
foreach_in_collection celln  [get_references -hierarchical c2p1_*] {
foreach_in_collection celln  [get_references -hierarchical c2p1_*] {
    set_disable_timing [get_object_name $celln]/U2 -from B -to Z
    set_disable_timing [get_object_name $celln]/U2 -from B -to Z
    set_disable_timing [get_object_name $celln]/U3 -from B -to Z
    set_disable_timing [get_object_name $celln]/U3 -from B -to Z
}
}
 
# It is not a problem if MRMA is not used in the design.
 
 
# tarb
# tarb
foreach_in_collection celln  [get_references -hierarchical tarb_*] {
foreach_in_collection celln  [get_references -hierarchical tarb_*] {
    set_disable_timing [get_object_name $celln]/U2 -from A -to Z
    set_disable_timing [get_object_name $celln]/U2 -from A -to Z
    set_disable_timing [get_object_name $celln]/U3 -from A -to Z
    set_disable_timing [get_object_name $celln]/U3 -from A -to Z
}
}
 
# It is not a problem if tree arbiter is not used in the design.
 
 
# cr_blk
# cr_blk
foreach_in_collection celln  [get_references -hierarchical cr_blk_*] {
foreach_in_collection celln  [get_references -hierarchical cr_blk_*] {
    set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
    set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z
}
}
 
# It is not a problem if MRMA is not used in the design.
 
 
 
# dcb data crossbar
 
foreach_in_collection celln  [get_references -hierarchical dcb_*] {
 
    set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
 
}
 
 
 
# dcb data crossbar
 
foreach_in_collection celln  [get_references -hierarchical rcb_*] {
 
    set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
 
}
 
#It is not a problem if there is no rcb modules in the design.
 
 
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