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*** SystemVerilog is used ***
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*** SystemVerilog is used ***
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History:
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History:
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05/05/2009 Initial version. <wsong83@gmail.com>
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05/05/2009 Initial version. <wsong83@gmail.com>
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17/04/2011 Replace the common ack generation. <wsong83@gmail.com>
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17/04/2011 Replace the common ack generation. <wsong83@gmail.com>
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23/05/2011 Clean up for opensource. <wsong83@gmail.com>
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26/05/2011 Clean up for opensource. <wsong83@gmail.com>
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*/
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*/
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// the router structure definitions
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// the router structure definitions
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`include "define.v"
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`include "define.v"
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output [SCN-1:0] o0, o1, o2, o3;
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output [SCN-1:0] o0, o1, o2, o3;
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input oa; // input ack
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input oa; // input ack
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output ia; // output ack
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output ia; // output ack
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`ifdef ENABLE_EOF
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`ifdef ENABLE_EOF
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input o4; // the eof bit
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output o4; // the eof bit
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output i4;
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input i4;
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`endif
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`endif
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// internal signals
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// internal signals
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wire [2*SCN-2:0] tack;
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wire [SCN-1:0] tack;
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// generate the ack line
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// generate the ack line
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genvar i;
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genvar i;
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// the data pipe stage
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// the data pipe stage
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dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i]));
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dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i]));
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end endgenerate
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end endgenerate
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// the eof bit
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// the eof bit
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`ifdef ENABLE_EOF
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`ifdef ENABLE_EOF
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dc2 DD_DC4 (.d(i4), .a(oa[SCN-1]), .q(o4));
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dc2 DD_DC4 (.d(i4), .a(oa), .q(o4));
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`endif
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`endif
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// generate the input ack
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// generate the input ack
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assign tack = o0|o1|o2|o3;
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assign tack = o0|o1|o2|o3;
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ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia));
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ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia));
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