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Line 22... |
module inpbuf (/*AUTOARG*/
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module inpbuf (/*AUTOARG*/
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// Outputs
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// Outputs
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dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
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dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
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// Inputs
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// Inputs
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di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
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di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
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rstn
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rst_n
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);
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);
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parameter DW = 32; // data width
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parameter DW = 32; // data width
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parameter VCN = 2; // VC number
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parameter VCN = 2; // VC number
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parameter DIR = 0; // 0-4 south, west, north, east, local
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parameter DIR = 0; // 0-4 south, west, north, east, local
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Line 62... |
input [VCN-1:0][SN-1:0] swrt;
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input [VCN-1:0][SN-1:0] swrt;
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// local addresses
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// local addresses
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input [7:0] addrx, addry;
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input [7:0] addrx, addry;
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input rstn;
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input rst_n;
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//-----------------------------
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//-----------------------------
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// VC_MUX
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// VC_MUX
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wire ivma, rua;
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wire ivma, rua;
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wire [SCN-1:0] di0m, di1m, di2m, di3m;
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wire [SCN-1:0] di0m, di1m, di2m, di3m;
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| Line 115... |
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);
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);
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//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
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//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
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ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
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ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
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assign di0m = rstn ? di0 : 0;
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assign di0m = rst_n ? di0 : 0;
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assign di1m = rstn ? di1 : 0;
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assign di1m = rst_n ? di1 : 0;
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assign di2m = rstn ? di2 : 0;
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assign di2m = rst_n ? di2 : 0;
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assign di3m = rstn ? di3 : 0;
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assign di3m = rst_n ? di3 : 0;
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assign ditm = rstn ? dit : 0;
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assign ditm = rst_n ? dit : 0;
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assign divcm = rstn ? divc : 0;
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assign divcm = rst_n ? divc : 0;
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//---------------------------------------------
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//---------------------------------------------
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// the VC buffers
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// the VC buffers
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generate
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generate
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for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
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for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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);
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);
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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end // block: SC
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end // block: SC
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pipen #(.DW(FT))
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pipen #(.DW(FT))
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TP (
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TP (
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.d_in ( vcdt[gbd][gvc] ),
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.d_in ( vcdt[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out_a ( vcdatn[gbd+1][gvc] )
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.d_out_a ( vcdatn[gbd+1][gvc] )
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);
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);
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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end // block: V
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end // block: V
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end // block: BFN
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end // block: BFN
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for(gvc=0; gvc<VCN; gvc++) begin:BFNV
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for(gvc=0; gvc<VCN; gvc++) begin:BFNV
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i1 ( vcd1[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i2 ( vcd2[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.i3 ( vcd3[gbd][gvc][gsub] ),
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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.oa ( vcdadn[gbd+1][gvc][gsub] )
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);
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);
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
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assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
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end // block: SC
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end // block: SC
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pipen #(.DW(FT))
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pipen #(.DW(FT))
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TP (
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TP (
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.d_in ( vcdt[gbd][gvc] ),
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.d_in ( vcdt[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_in_a ( vcdat[gbd][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out ( vcdt[gbd+1][gvc] ),
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.d_out_a ( vcdatn[gbd+1][gvc] )
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.d_out_a ( vcdatn[gbd+1][gvc] )
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);
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);
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
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assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
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pipen #(.DW(2))
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pipen #(.DW(2))
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CTP (
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CTP (
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.d_in ( vcft[gbd][gvc] ),
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.d_in ( vcft[gbd][gvc] ),
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.d_in_a ( vcfta[gbd][gvc] ),
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.d_in_a ( vcfta[gbd][gvc] ),
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.d_out ( vcft[gbd+1][gvc] ),
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.d_out ( vcft[gbd+1][gvc] ),
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.d_out_a ( vcftan[gbd+1][gvc] )
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.d_out_a ( vcftan[gbd+1][gvc] )
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);
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);
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assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rstn;
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assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
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end // block: V
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end // block: V
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end // block: BFL2
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end // block: BFL2
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for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
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for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
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ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
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ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
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| Line 231... |
Line 231... |
pipen #(.DW(SN))
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pipen #(.DW(SN))
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RP (
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RP (
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.d_in ( swrt[gvc] ),
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.d_in ( swrt[gvc] ),
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.d_in_a ( swa[gvc] ),
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.d_in_a ( swa[gvc] ),
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.d_out ( rtg[gvc] ),
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.d_out ( rtg[gvc] ),
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.d_out_a ( (~vcda[1][gvc])&rstn )
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.d_out_a ( (~vcda[1][gvc])&rst_n )
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);
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);
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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for(gvc=0; gvc<VCN; gvc++) begin:LPS
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for(gvc=0; gvc<VCN; gvc++) begin:LPS
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// credit control
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// credit control
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dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rstn));
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dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
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// output name conversation
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// output name conversation
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assign do0[gvc] = vcd0[PD*2][gvc];
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assign do0[gvc] = vcd0[PD*2][gvc];
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assign do1[gvc] = vcd1[PD*2][gvc];
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assign do1[gvc] = vcd1[PD*2][gvc];
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assign do2[gvc] = vcd2[PD*2][gvc];
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assign do2[gvc] = vcd2[PD*2][gvc];
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| Line 261... |
Line 261... |
// routing unit
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// routing unit
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rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(2))
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rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(2))
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RTC (
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RTC (
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.dia ( rua ),
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.dia ( rua ),
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.dort ( vcr ),
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.dort ( vcr ),
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.rstn ( rstn ),
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.rst_n ( rst_n ),
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.di0 ( di0m[3:0] ),
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.di0 ( di0m[3:0] ),
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.di1 ( di1m[3:0] ),
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.di1 ( di1m[3:0] ),
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.di2 ( di2m[3:0] ),
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.di2 ( di2m[3:0] ),
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.di3 ( di3m[3:0] ),
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.di3 ( di3m[3:0] ),
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.dit ( ditm ),
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.dit ( ditm ),
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